From: Dave Jiang <dave.jiang@intel.com>
To: djbw@fb.com
Cc: vinod.koul@intel.com, linux-kernel@vger.kernel.org
Subject: [PATCH 05/10] ioatdma: skip legacy reset bits since v3.3 plattform doesn't need it
Date: Tue, 26 Mar 2013 15:42:59 -0700 [thread overview]
Message-ID: <20130326224259.15072.83663.stgit@djiang5-linux2.ch.intel.com> (raw)
In-Reply-To: <20130326223953.15072.26605.stgit@djiang5-linux2.ch.intel.com>
Make it so only 3.2 and earlier platform need the PCI config register
clearings since this implementation does not have the registers.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/dma/ioat/dma_v3.c | 34 +++++++++++++++++++++-------------
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index e66fead..c53204e 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -1339,20 +1339,28 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan)
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
- /* clear any pending errors */
- err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
- if (err) {
- dev_err(&pdev->dev, "channel error register unreachable\n");
- return err;
- }
- pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
+ if (device->version < IOAT_VER_3_3) {
+ /* clear any pending errors */
+ err = pci_read_config_dword(pdev,
+ IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
+ if (err) {
+ dev_err(&pdev->dev,
+ "channel error register unreachable\n");
+ return err;
+ }
+ pci_write_config_dword(pdev,
+ IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
- /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
- * (workaround for spurious config parity error after restart)
- */
- pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
- if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
- pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
+ /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
+ * (workaround for spurious config parity error after restart)
+ */
+ pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
+ if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
+ pci_write_config_dword(pdev,
+ IOAT_PCI_DMAUNCERRSTS_OFFSET,
+ 0x10);
+ }
+ }
err = ioat2_reset_sync(chan, msecs_to_jiffies(200));
if (err) {
next prev parent reply other threads:[~2013-03-26 22:43 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-26 22:42 [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Dave Jiang
2013-03-26 22:42 ` [PATCH 01/10] ioatdma: Adding PCI IDs for Intel Atom S1200 product family ioatdma devices Dave Jiang
2013-03-26 22:42 ` [PATCH 02/10] ioatdma: Add 64bit chansts register read for ioat v3.3 Dave Jiang
2013-03-26 22:42 ` [PATCH 03/10] ioatdma: channel reset scheme fixup on Intel Atom S1200 platforms Dave Jiang
2013-03-26 22:42 ` [PATCH 04/10] ioatdma: Removing hw bug workaround for CB3.x .2 and earlier Dave Jiang
2013-03-26 22:42 ` Dave Jiang [this message]
2013-03-26 22:43 ` [PATCH 06/10] ioatdma: Removing PQ val disable for cb3.3 Dave Jiang
2013-03-27 18:48 ` Dan Williams
2013-03-29 17:31 ` Dave Jiang
2013-03-26 22:43 ` [PATCH 07/10] ioatdma: skip silicon bug workaround for pq_align " Dave Jiang
2013-03-26 22:43 ` [PATCH 08/10] ioatdma: Adding support for 16 src PQ ops and super extended descriptors Dave Jiang
2013-03-26 22:43 ` [PATCH 09/10] ioatdma: Adding write back descriptor error status support for ioatdma 3.3 Dave Jiang
2013-03-26 23:47 ` Dan Williams
2013-03-26 23:55 ` Dave Jiang
2013-03-28 22:25 ` [PATCH 09/10 v2] " Jiang, Dave
2013-03-26 22:43 ` [PATCH 10/10] ioatdma: S1200 platforms ioatdma channel 2 and 3 falsely advertise RAID cap Dave Jiang
2013-04-09 7:28 ` [PATCH 00/10] Add Intel Atom S1200 seris ioatdma support Vinod Koul
2013-04-10 0:56 ` Dan Williams
[not found] ` <CAA9_cmftcvYN_g0Sj12tMa4T8LxbPdk6wDxwkbTrgQPUUfc0FA@mail.gmail.com>
2013-04-10 5:00 ` Vinod Koul
2013-04-10 5:10 ` Vinod Koul
2013-04-10 5:33 ` Jiang, Dave
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