From: Ingo Molnar <mingo@kernel.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
akpm@linux-foundation.org, tglx@linutronix.de,
eranian@google.com, torvalds@linux-foundation.org
Subject: Re: Basic perf PMU support for Haswell v10
Date: Mon, 15 Apr 2013 12:36:39 +0200 [thread overview]
Message-ID: <20130415103639.GA25366@gmail.com> (raw)
In-Reply-To: <20130405064654.GA25936@gmail.com>
* Ingo Molnar <mingo@kernel.org> wrote:
>
> * Andi Kleen <andi@firstfloor.org> wrote:
>
> > This is based on v7 of the full Haswell PMU support,
>
> This series looks mostly good - I've got two requests:
>
> - please rename intx -> in_tx, INTX -> IN_TX, as 'intx' is confusing
>
> - please port to the latest tip:master (or perf/core), as the underlying
> code changed meanwhile, creating conflicts.
Any update here? If not done this week then you'll possibly miss v3.10 as
well.
Thanks,
Ingo
next prev parent reply other threads:[~2013-04-15 10:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-21 19:59 Basic perf PMU support for Haswell v10 Andi Kleen
2013-03-21 19:59 ` [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5 Andi Kleen
2013-05-31 13:02 ` Stephane Eranian
2013-05-31 16:23 ` Andi Kleen
2013-03-21 19:59 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v7 Andi Kleen
2013-03-21 19:59 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS support v4 Andi Kleen
2013-03-21 19:59 ` [PATCH 4/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-03-21 19:59 ` [PATCH 5/5] perf, x86: Support Haswell v4 LBR format Andi Kleen
2013-03-28 15:13 ` Basic perf PMU support for Haswell v10 Stephane Eranian
2013-04-05 6:46 ` Ingo Molnar
2013-04-15 10:36 ` Ingo Molnar [this message]
2013-05-27 13:01 ` Stephane Eranian
2013-05-27 19:18 ` Andi Kleen
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