From: Arnd Bergmann <arnd@arndb.de>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Jonathan Austin <jonathan.austin@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH v3] irqchip: Add support for ARMv7-M's NVIC
Date: Thu, 18 Apr 2013 11:01:13 +0200 [thread overview]
Message-ID: <201304181101.13644.arnd@arndb.de> (raw)
In-Reply-To: <20130418081555.GV30416@pengutronix.de>
On Thursday 18 April 2013, Uwe Kleine-König wrote:
> > > + * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
> > > + * 16 irqs.
> > > + */
> > > +#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
> >
> > Is this actually inherent to the hardware design, or is the number of irqs
> > actually customizable? Also, why do you care about the maximum? You only
> > use it to check against the device tree provided value, but I suppose
> > you could just as well trust that property to be correct.
> I don't provide a value for the number of irqs in the device tree. There
> is only the value INTLINESNUM in the V7M_SCS_ICTR register that is used
> to determine the number of interrupt banks.
Ah, right. But do you have any reason to believe it could be wrong?
Arnd
next prev parent reply other threads:[~2013-04-18 9:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-17 16:02 [PATCH v3] irqchip: Add support for ARMv7-M's NVIC Uwe Kleine-König
2013-04-17 20:23 ` Arnd Bergmann
2013-04-18 8:15 ` Uwe Kleine-König
2013-04-18 9:01 ` Arnd Bergmann [this message]
2013-04-18 9:24 ` Uwe Kleine-König
2013-04-18 9:38 ` Arnd Bergmann
2013-04-19 13:51 ` Uwe Kleine-König
2013-04-19 14:14 ` Arnd Bergmann
2013-04-18 9:35 ` Thomas Gleixner
2013-04-19 15:09 ` Uwe Kleine-König
2013-04-22 10:02 ` Uwe Kleine-König
2013-04-22 12:04 ` Arnd Bergmann
2013-04-22 13:50 ` Thomas Gleixner
2013-04-22 14:21 ` Thomas Gleixner
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