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* [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value
@ 2013-05-14 13:14 Ulf Hansson
  2013-05-14 14:40 ` Lee Jones
  0 siblings, 1 reply; 2+ messages in thread
From: Ulf Hansson @ 2013-05-14 13:14 UTC (permalink / raw)
  To: Samuel Ortiz, linux-kernel, linux-arm-kernel
  Cc: Lee Jones, Linus Walleij, Ulf Hansson, Paer-Olof Haakansson

From: Ulf Hansson <ulf.hansson@linaro.org>

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework were enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Cc: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/db8500-prcmu.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 5389368..66f8097 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n)
 
 	if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
 		divsel = dsiclk[n].divsel;
+	else
+		dsiclk[n].divsel = divsel;
 
 	switch (divsel) {
 	case PRCM_DSI_PLLOUT_SEL_PHI_4:
-- 
1.7.10


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value
  2013-05-14 13:14 [PATCH] mfd: db8500-prcmu: Update stored DSI PLL divider value Ulf Hansson
@ 2013-05-14 14:40 ` Lee Jones
  0 siblings, 0 replies; 2+ messages in thread
From: Lee Jones @ 2013-05-14 14:40 UTC (permalink / raw)
  To: Ulf Hansson
  Cc: Samuel Ortiz, linux-kernel, linux-arm-kernel, Linus Walleij,
	Ulf Hansson, Paer-Olof Haakansson

On Tue, 14 May 2013, Ulf Hansson wrote:

> From: Ulf Hansson <ulf.hansson@linaro.org>
> 
> Previously the DSI PLL divider rate was initialised statically and
> assumed to be 1. Before the common clock framework were enabled for
> ux500, a call to clk_set_rate() would always update the HW registers
> no matter what the current setting was.
> 
> This patch makes sure the actual hw settings and the sw assumed
> settings are matched.
> 
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Paer-Olof Haakansson <par-olof.hakansson@stericsson.com>
> Cc: Lee Jones <lee.jones@linaro.org>
> ---
>  drivers/mfd/db8500-prcmu.c |    2 ++
>  1 file changed, 2 insertions(+)

I understand that this is causing an issue for the Multimedia guys who
use this. As it's causing an issue and you are 'the' ST-E clock guru,
I'll tentatively apply this to my v3.10 -fixes branch.

If anyone has any arguments against it, please step forward.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 2+ messages in thread

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