[PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[Doug Anderson]

The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations.  Fix our rate
recalculation to do this correctly.

Before doing this, I tried setting EPLL on exynos5250 to:
  rate, m, p, s, k = 80000000, 107, 2, 4, 43691

This rate is exactly from the table in the exynos5250 user manual.

I read this back as 80750003 with:
  cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

After this patch, it reads back as 80000003

  mw 0x10020130 a06b0204
  mw 0x10020134 0000aaab

Signed-off-by: Doug Anderson <dianders@chromium.org>
---
This patch is based upon another in-flight patch to avoid conflicts:
  clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx
  https://patchwork.kernel.org/patch/2629751/

 drivers/clk/samsung/clk-pll.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 01f17cf..26416bb 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -115,7 +115,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
 	struct samsung_clk_pll *pll = to_clk_pll(hw);
-	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	s16 kdiv;
 	u64 fvco = parent_rate;
 
 	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
@@ -123,7 +124,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
-	kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+	kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
 
 	fvco *= (mdiv << 16) + kdiv;
 	do_div(fvco, (pdiv << sdiv));
-- 
1.8.2.1

Re: [PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[Vikas Sajjan]

Hi Doug,

Looks good to me.

On 1 June 2013 00:28, Doug Anderson <dianders@chromium.org> wrote:
> The KDIV value is often listed as unsigned but it needs to be treated
> as a 16-bit signed value when using it in calculations.  Fix our rate
> recalculation to do this correctly.
>
> Before doing this, I tried setting EPLL on exynos5250 to:
>   rate, m, p, s, k = 80000000, 107, 2, 4, 43691
>
> This rate is exactly from the table in the exynos5250 user manual.
>
> I read this back as 80750003 with:
>   cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate
>
> After this patch, it reads back as 80000003
>
>   mw 0x10020130 a06b0204
>   mw 0x10020134 0000aaab
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>


Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org>


> ---
> This patch is based upon another in-flight patch to avoid conflicts:
>   clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx
>   https://patchwork.kernel.org/patch/2629751/
>
>  drivers/clk/samsung/clk-pll.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 01f17cf..26416bb 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -115,7 +115,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
>                                 unsigned long parent_rate)
>  {
>         struct samsung_clk_pll *pll = to_clk_pll(hw);
> -       u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
> +       u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
> +       s16 kdiv;
>         u64 fvco = parent_rate;
>
>         pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
> @@ -123,7 +124,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
>         mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
>         pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
>         sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
> -       kdiv = pll_con1 & PLL36XX_KDIV_MASK;
> +       kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
>
>         fvco *= (mdiv << 16) + kdiv;
>         do_div(fvco, (pdiv << sdiv));
> --
> 1.8.2.1
>



--
Thanks and Regards
 Vikas Sajjan

RE: [PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[Kukjin Kim]

Doug Anderson wrote:
> 
> The KDIV value is often listed as unsigned but it needs to be treated
> as a 16-bit signed value when using it in calculations.  Fix our rate
> recalculation to do this correctly.
> 
> Before doing this, I tried setting EPLL on exynos5250 to:
>   rate, m, p, s, k = 80000000, 107, 2, 4, 43691
> 
> This rate is exactly from the table in the exynos5250 user manual.
> 
> I read this back as 80750003 with:
>   cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate
> 
> After this patch, it reads back as 80000003
> 
>   mw 0x10020130 a06b0204
>   mw 0x10020134 0000aaab
> 
> Signed-off-by: Doug Anderson <dianders@chromium.org>

Yeah,

Acked-by: Kukjin Kim <kgene.kim@samsung.com>

Mike, please apply in your fixes.

Thanks.

- Kukjin

> ---
> This patch is based upon another in-flight patch to avoid conflicts:
>   clk: samsung: Use clk->base instead of directly using clk->con0 for
> PLL3xxx
>   https://patchwork.kernel.org/patch/2629751/
> 
>  drivers/clk/samsung/clk-pll.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 01f17cf..26416bb 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -115,7 +115,8 @@ static unsigned long
> samsung_pll36xx_recalc_rate(struct clk_hw *hw,
>  				unsigned long parent_rate)
>  {
>  	struct samsung_clk_pll *pll = to_clk_pll(hw);
> -	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
> +	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
> +	s16 kdiv;
>  	u64 fvco = parent_rate;
> 
>  	pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
> @@ -123,7 +124,7 @@ static unsigned long
> samsung_pll36xx_recalc_rate(struct clk_hw *hw,
>  	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
>  	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
>  	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
> -	kdiv = pll_con1 & PLL36XX_KDIV_MASK;
> +	kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
> 
>  	fvco *= (mdiv << 16) + kdiv;
>  	do_div(fvco, (pdiv << sdiv));
> --
> 1.8.2.1

Re: RE: [PATCH] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[Mike Turquette]

Quoting Kukjin Kim (2013-06-05 04:51:29)
> Doug Anderson wrote:
> > 
> > The KDIV value is often listed as unsigned but it needs to be treated
> > as a 16-bit signed value when using it in calculations.  Fix our rate
> > recalculation to do this correctly.
> > 
> > Before doing this, I tried setting EPLL on exynos5250 to:
> >   rate, m, p, s, k = 80000000, 107, 2, 4, 43691
> > 
> > This rate is exactly from the table in the exynos5250 user manual.
> > 
> > I read this back as 80750003 with:
> >   cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate
> > 
> > After this patch, it reads back as 80000003
> > 
> >   mw 0x10020130 a06b0204
> >   mw 0x10020134 0000aaab
> > 
> > Signed-off-by: Doug Anderson <dianders@chromium.org>
> 
> Yeah,
> 
> Acked-by: Kukjin Kim <kgene.kim@samsung.com>
> 
> Mike, please apply in your fixes.
> 
> Thanks.
> 
> - Kukjin
> 
> > ---
> > This patch is based upon another in-flight patch to avoid conflicts:
> >   clk: samsung: Use clk->base instead of directly using clk->con0 for
> > PLL3xxx
> >   https://patchwork.kernel.org/patch/2629751/

The dependency series is not destined for clk-fixes but Kukjin has
requested this patch as a fix.  If you want this patch as a fix can you
rebase it against:

git://git.linaro.org/people/mturquette/linux.git clk-fixes

Thanks,
Mike

> > 
> >  drivers/clk/samsung/clk-pll.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> > index 01f17cf..26416bb 100644
> > --- a/drivers/clk/samsung/clk-pll.c
> > +++ b/drivers/clk/samsung/clk-pll.c
> > @@ -115,7 +115,8 @@ static unsigned long
> > samsung_pll36xx_recalc_rate(struct clk_hw *hw,
> >                               unsigned long parent_rate)
> >  {
> >       struct samsung_clk_pll *pll = to_clk_pll(hw);
> > -     u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
> > +     u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
> > +     s16 kdiv;
> >       u64 fvco = parent_rate;
> > 
> >       pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
> > @@ -123,7 +124,7 @@ static unsigned long
> > samsung_pll36xx_recalc_rate(struct clk_hw *hw,
> >       mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
> >       pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
> >       sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
> > -     kdiv = pll_con1 & PLL36XX_KDIV_MASK;
> > +     kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
> > 
> >       fvco *= (mdiv << 16) + kdiv;
> >       do_div(fvco, (pdiv << sdiv));
> > --
> > 1.8.2.1

[PATCH v2] clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly

[Doug Anderson]

The KDIV value is often listed as unsigned but it needs to be treated
as a 16-bit signed value when using it in calculations.  Fix our rate
recalculation to do this correctly.

Before doing this, I tried setting EPLL on exynos5250 to:
  rate, m, p, s, k = 80000000, 107, 2, 4, 43691

This rate is exactly from the table in the exynos5250 user manual.

I read this back as 80750003 with:
  cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate

After this patch, it reads back as 80000003

Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org>
---
Changes in v2:
- Rebased against mturquette/linux.git clk-fixes

 drivers/clk/samsung/clk-pll.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..362f12d 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -111,7 +111,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 				unsigned long parent_rate)
 {
 	struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
-	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
+	s16 kdiv;
 	u64 fvco = parent_rate;
 
 	pll_con0 = __raw_readl(pll->con_reg);
@@ -119,7 +120,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
-	kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+	kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
 
 	fvco *= (mdiv << 16) + kdiv;
 	do_div(fvco, (pdiv << sdiv));
-- 
1.8.3