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From: Mike Turquette <mturquette@linaro.org>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/2] PLL m,n,p init from SoC files
Date: Tue, 11 Jun 2013 17:39:51 -0700	[thread overview]
Message-ID: <20130612003951.8816.41684@quantum> (raw)
In-Reply-To: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com>

Quoting Peter De Schrijver (2013-06-05 06:51:24)
> The m,n,p fields don't have the same bit offset and width across all PLLs.
> This patchset allows SoC specific files to indicate the offset and width.
> It also provides the data for Tegra114.
> 

Taken into clk-next.

Thanks,
Mike

> Peter De Schrijver (2):
>   clk: tegra: allow PLL m,n,p init from SoC files
>   clk: tegra: PLL m,n,p init for Tegra114
> 
>  drivers/clk/tegra/clk-pll.c      |   60 ++++++++++++++++-------------
>  drivers/clk/tegra/clk-tegra114.c |   77 ++++++++++++++++++++++++++++++++++++++
>  drivers/clk/tegra/clk.h          |   32 ++++++++++------
>  3 files changed, 130 insertions(+), 39 deletions(-)
> 
> -- 
> 1.7.7.rc0.72.g4b5ea.dirty

      parent reply	other threads:[~2013-06-12  0:39 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-05 13:51 [PATCH 0/2] PLL m,n,p init from SoC files Peter De Schrijver
2013-06-05 13:51 ` [PATCH 1/2] clk: tegra: allow " Peter De Schrijver
2013-06-05 13:51 ` [PATCH 2/2] clk: tegra: PLL m,n,p init for Tegra114 Peter De Schrijver
2013-06-05 13:54 ` [PATCH 0/2] PLL m,n,p init from SoC files Peter De Schrijver
2013-06-05 16:25 ` Stephen Warren
2013-06-12  0:39 ` Mike Turquette [this message]

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