Re: [PATCH 1/8] perf,x86: disable PEBS-LL in intel_pmu_pebs_disable()

[Peter Zijlstra <peterz@infradead.org>]

On Fri, Jun 21, 2013 at 04:20:41PM +0200, Stephane Eranian wrote:
> Make sure intel_pmu_pebs_disable() and intel_pmu_pebs_enable()
> are symmetrical w.r.t. PEBS-LL and precise store.
> 
> Signed-off-by: Stephane Eranian <eranian@google.com>

This seems unrelated to the actual patch series and should still go in.


> ---
>  arch/x86/kernel/cpu/perf_event_intel_ds.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index ed3e553..3065c57 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -653,6 +653,12 @@ void intel_pmu_pebs_disable(struct perf_event *event)
>  	struct hw_perf_event *hwc = &event->hw;
>  
>  	cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
> +
> +	if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
> +		cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
> +	else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
> +		cpuc->pebs_enabled &= ~(1ULL << 63);
> +
>  	if (cpuc->enabled)
>  		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
>  
> -- 
> 1.8.1.2
>