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From: Ingo Molnar <mingo@kernel.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, eranian@google.com,
	peterz@infradead.org, Andi Kleen <ak@linux.jf.intel.com>
Subject: Re: [PATCH] perf, x86: Support full width counting v3
Date: Tue, 25 Jun 2013 09:23:38 +0200	[thread overview]
Message-ID: <20130625072338.GA12190@gmail.com> (raw)
In-Reply-To: <20130625072212.GA11420@gmail.com>


* Ingo Molnar <mingo@kernel.org> wrote:

> Looks good - the changelog needs more work: please first outline the 
> current behavior (how we can only write 32 bit values into the counter, 
> even though the counter range is larger on most CPUs).
> 
> Then also outline the Haswell problems more precisely. What happens, 
> why, with what probability and why do we care?

For the latter it's enough to put a reference like this into the 
changelog:

  See the patch "perf/x86/intel: Avoid checkpointed counters causing 
  excessive TSX aborts" for more details.

Thanks,

	Ingo

      reply	other threads:[~2013-06-25  7:23 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1372121749-12164-1-git-send-email-andi@firstfloor.org>
2013-06-25  7:22 ` [PATCH] perf, x86: Support full width counting v3 Ingo Molnar
2013-06-25  7:23   ` Ingo Molnar [this message]

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