From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751775Ab3FYRxM (ORCPT ); Tue, 25 Jun 2013 13:53:12 -0400 Received: from mail.skyhub.de ([78.46.96.112]:49466 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751455Ab3FYRxK (ORCPT ); Tue, 25 Jun 2013 13:53:10 -0400 Date: Tue, 25 Jun 2013 19:53:06 +0200 From: Borislav Petkov To: "Naveen N. Rao" Cc: tony.luck@intel.com, ananth@in.ibm.com, masbock@linux.vnet.ibm.com, lcm@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, ying.huang@intel.com Subject: Re: [PATCH v2 1/2] mce: acpi/apei: Honour Firmware First for MCA banks listed in APEI HEST CMC Message-ID: <20130625175306.GE4855@pd.tnic> References: <20130621174057.GI22006@pd.tnic> <20130625174536.5226.66421.stgit@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20130625174536.5226.66421.stgit@localhost.localdomain> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 25, 2013 at 11:16:32PM +0530, Naveen N. Rao wrote: > Tony, Boris, > Can you please see if the comments in the below patch include the details you > were expecting? > > Thanks, > Naveen > > -- > Add comments to clarify usage of the various bitfields in the MCA subsystem > > Signed-off-by: Naveen N. Rao > --- > arch/x86/kernel/cpu/mcheck/mce.c | 5 ++++- > arch/x86/kernel/cpu/mcheck/mce_intel.c | 9 +++++++++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c > index 9239504..bf49cdb 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce.c > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > @@ -89,7 +89,10 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); > static DEFINE_PER_CPU(struct mce, mces_seen); > static int cpu_missing; > > -/* MCA banks polled by the period polling timer for corrected events */ > +/* > + * MCA banks polled by the period polling timer for corrected events. > + * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). > + */ > DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { > [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL > }; > diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c > index ae1697c..2816f53 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c > +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c > @@ -24,6 +24,15 @@ > * Also supports reliable discovery of shared banks. > */ > > +/* > + * Indicates MCA banks controlled by the current cpu for CMCI. Note that this > + * can change when a cpu is offlined or brought online since some MCA banks > + * are shared across cpus. When a cpu is offlined, cmci_clear() disables CMCI > + * on all banks owned by the cpu and clears this bitfield. At this point, > + * cmci_rediscover() kicks in and a different cpu may end up taking > + * ownership of some of the shared MCA banks that were previously owned > + * by the offlined cpu. > + */ > static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); Yep, it looks ok to me. Acked-by: Borislav Petkov Thanks. -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. --