From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Wolfram Sang <wsa@the-dreams.de>
Cc: Chew Chiau Ee <chiaue.ee.chew@intel.com>,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
Christian Ruppert <christian.ruppert@abilis.com>
Subject: Re: [PATCH] i2c-designware: Manually set RESTART bit between messages
Date: Thu, 4 Jul 2013 10:41:21 +0300 [thread overview]
Message-ID: <20130704074121.GD4898@intel.com> (raw)
In-Reply-To: <20130703201510.GB2958@katana>
On Wed, Jul 03, 2013 at 10:15:11PM +0200, Wolfram Sang wrote:
>
> CCing Mika and Christian.
>
> On Fri, Jun 21, 2013 at 03:05:28PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
> >
> > If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the
> > Designware I2C controller doesn't generate RESTART unless user specifically
> > requests it by setting RESTART bit in IC_DATA_CMD register.
> >
> > Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from hardware
> > register, we must always manually set the restart bit between messages.
> >
> > Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> How come restart has worked before? Or did it not?
It works fine. However IC_EMPTYFIFO_HOLD_MASTER_EN=1 makes a difference. We
had similar thing with the STOP that was fixed previously.
If I understand the dw i2c databook right, RESTART is only issued if the
transfer direction changes. So if you have two or more consecutive
transfers that have the same direction (not sure how common that is) there
is no RESTART between them unless DW_IC_CON_RESTART_EN is set.
Chiau Ee, does this fix a real problem?
next prev parent reply other threads:[~2013-07-04 7:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-21 7:05 [PATCH] i2c-designware: Manually set RESTART bit between messages Chew Chiau Ee
2013-07-03 20:15 ` Wolfram Sang
2013-07-04 7:41 ` Mika Westerberg [this message]
2013-07-16 3:27 ` Chew, Chiau Ee
2013-08-07 14:28 ` Wolfram Sang
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