[PATCH] x86: add pin control support to Intel low power subsystem

[PATCH] x86: add pin control support to Intel low power subsystem

[Mathias Nyman]

x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol functions
such as pin muxing and grouping are possible to add later.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
---
 arch/x86/Kconfig |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 30c40f0..91f72b5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -482,11 +482,12 @@ config X86_INTEL_LPSS
 	bool "Intel Low Power Subsystem Support"
 	depends on ACPI
 	select COMMON_CLK
+	select PINCTRL
 	---help---
 	  Select to build support for Intel Low Power Subsystem such as
 	  found on Intel Lynxpoint PCH. Selecting this option enables
-	  things like clock tree (common clock framework) which are needed
-	  by the LPSS peripheral drivers.
+	  things like clock tree (common clock framework) and pincontrol
+	  which are needed by the LPSS peripheral drivers.
 
 config X86_RDC321X
 	bool "RDC R-321x SoC"
-- 
1.7.4.1

Re: [PATCH] x86: add pin control support to Intel low power subsystem

[Mika Westerberg]

On Fri, Sep 13, 2013 at 05:02:29PM +0300, Mathias Nyman wrote:
> x86 chips with LPSS (low power subsystem) such as Lynxpoint and
> Baytrail have SoC like peripheral support and controllable pins.
> 
> At the moment, Baytrail needs the pinctrl-baytrail driver to let
> peripherals control their gpio resources, but more pincontrol functions
> such as pin muxing and grouping are possible to add later.
> 
> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>

Makes sense, and since there seems to be no way to enable pinctrl by
just selecting it from 'make XXXconfig',

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>

[tip:x86/urgent] x86/intel/lpss: Add pin control support to Intel low power subsystem

[tip-bot for Mathias Nyman]

Commit-ID:  0f531431d3de88efb4234d6c0ce22089ec035a38
Gitweb:     http://git.kernel.org/tip/0f531431d3de88efb4234d6c0ce22089ec035a38
Author:     Mathias Nyman <mathias.nyman@linux.intel.com>
AuthorDate: Fri, 13 Sep 2013 17:02:29 +0300
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Sat, 14 Sep 2013 08:06:28 +0200

x86/intel/lpss: Add pin control support to Intel low power subsystem

x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol
functions such as pin muxing and grouping are possible to add
later.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: http://lkml.kernel.org/r/1379080949-21734-1-git-send-email-mathias.nyman@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/Kconfig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b32ebf9..4d5843d 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -482,11 +482,12 @@ config X86_INTEL_LPSS
 	bool "Intel Low Power Subsystem Support"
 	depends on ACPI
 	select COMMON_CLK
+	select PINCTRL
 	---help---
 	  Select to build support for Intel Low Power Subsystem such as
 	  found on Intel Lynxpoint PCH. Selecting this option enables
-	  things like clock tree (common clock framework) which are needed
-	  by the LPSS peripheral drivers.
+	  things like clock tree (common clock framework) and pincontrol
+	  which are needed by the LPSS peripheral drivers.
 
 config X86_RDC321X
 	bool "RDC R-321x SoC"