From: Borislav Petkov <bp@alien8.de>
To: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: dougthompson@xmission.com, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors
Date: Fri, 7 Feb 2014 15:01:44 +0100 [thread overview]
Message-ID: <20140207140144.GI24395@pd.tnic> (raw)
In-Reply-To: <1390338216-3873-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
On Tue, Jan 21, 2014 at 03:03:36PM -0600, Aravind Gopalakrishnan wrote:
> The current logic that returns (sys_addr >> 8) & 0x7 when
> num_dcts_intlv = 4 is incorrect. We should really be doing-
> If intlv_addr = 0x4, then interleave on bits [9:8] and if
> intlv_addr = 0x5, interleave on bits [10:9].
>
> Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
> (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
>
> Tested on F15 M30h with mce_inj module and patch did not cause
> any regressions.
>
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Applied, thanks.
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
prev parent reply other threads:[~2014-02-07 14:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 21:03 [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors Aravind Gopalakrishnan
2014-02-03 19:10 ` Aravind Gopalakrishnan
2014-02-03 19:32 ` Borislav Petkov
2014-02-03 19:37 ` Aravind Gopalakrishnan
2014-02-07 14:01 ` Borislav Petkov [this message]
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