From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760166AbaCTXdi (ORCPT ); Thu, 20 Mar 2014 19:33:38 -0400 Received: from top.free-electrons.com ([176.31.233.9]:53185 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1759420AbaCTXdg (ORCPT ); Thu, 20 Mar 2014 19:33:36 -0400 Date: Fri, 21 Mar 2014 00:33:33 +0100 From: Alexandre Belloni To: Sebastian Hesselbarth Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Antoine Tenart , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] ARM: berlin: add scu and chipctrl device nodes for BG2/BG2Q Message-ID: <20140320233333.GY12021@piout.net> References: <1395347986-30203-1-git-send-email-sebastian.hesselbarth@gmail.com> <1395347986-30203-2-git-send-email-sebastian.hesselbarth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1395347986-30203-2-git-send-email-sebastian.hesselbarth@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/03/2014 at 21:39:45 +0100, Sebastian Hesselbarth wrote : > This adds scu and general purpose registers device nodes required for > SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump > address from general purpose (SW generic) register 1. > > Signed-off-by: Sebastian Hesselbarth Acked-by: Alexandre Belloni > --- > Cc: Rob Herring > Cc: Pawel Moll > Cc: Mark Rutland > Cc: Ian Campbell > Cc: Kumar Gala > Cc: Russell King > Cc: Antoine Tenart > Cc: Alexandre Belloni > Cc: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/arm/boot/dts/berlin2.dtsi | 10 ++++++++++ > arch/arm/boot/dts/berlin2q.dtsi | 10 ++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi > index 56a1af2f1052..4d85312dc17a 100644 > --- a/arch/arm/boot/dts/berlin2.dtsi > +++ b/arch/arm/boot/dts/berlin2.dtsi > @@ -72,6 +72,11 @@ > cache-level = <2>; > }; > > + scu: snoop-control-unit@ad0000 { > + compatible = "arm,cortex-a9-scu"; > + reg = <0xad0000 0x58>; > + }; > + > gic: interrupt-controller@ad1000 { > compatible = "arm,cortex-a9-gic"; > reg = <0xad1000 0x1000>, <0xad0100 0x0100>; > @@ -176,6 +181,11 @@ > }; > }; > > + generic-regs@ea0184 { > + compatible = "marvell,berlin-generic-regs", "syscon"; > + reg = <0xea0184 0x10>; > + }; > + > apb@fc0000 { > compatible = "simple-bus"; > #address-cells = <1>; > diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi > index 07452a7483fa..86d8a2c49f38 100644 > --- a/arch/arm/boot/dts/berlin2q.dtsi > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -87,6 +87,11 @@ > cache-level = <2>; > }; > > + scu: snoop-control-unit@ad0000 { > + compatible = "arm,cortex-a9-scu"; > + reg = <0xad0000 0x58>; > + }; > + > local-timer@ad0600 { > compatible = "arm,cortex-a9-twd-timer"; > reg = <0xad0600 0x20>; > @@ -183,6 +188,11 @@ > }; > }; > > + generic-regs@ea0110 { > + compatible = "marvell,berlin-generic-regs", "syscon"; > + reg = <0xea0110 0x10>; > + }; > + > apb@fc0000 { > compatible = "simple-bus"; > #address-cells = <1>; > -- > 1.9.0 > -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com