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Date: Mon, 24 Mar 2014 10:24:37 +0100
From: Ingo Molnar <mingo@kernel.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
        linux-kernel@vger.kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [GIT PULL] x86/apic changes for v3.14
Message-ID: <20140324092437.GA9344@gmail.com>
References: <20140120134220.GA12050@gmail.com>
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* Maciej W. Rozycki <macro@linux-mips.org> wrote:

> IMPLICATION: There is a possibility of clearing the Error register 
> status since the write to the register is not specifically blocked.
> 
> WORKAROUND: Writes should not occur to the Pentium processor APIC 
> Error register.
> 
> STATUS: For the steppings affected see the Summary Table of Changes 
> at the beginning of this section."
> 
> The steppings affected are actually: B1, B3 and B5.  Do we want to 
> keep supporting them?  I think yes, we already handle the erratum 
> elsewhere (lapic_setup_esr).  So how about:
> 
> 	if (lapic_get_maxlvt() > 3)	/* Due to the Pentium erratum 3AP. */
> 		apic_write(APIC_ESR, 0);
> 	v = apic_read(APIC_ESR);
> 
> instead?  I can make a patch if that would make your life easier.

Sure, a patch would be helpful.

>  There's room for optimisation here, but I think it's not worth the 
> effort as this is a slow path, APIC error interrupts are not 
> supposed to happen and are I believe extremely uncommon with FSB 
> message delivery.

Agreed.

Thanks,

	Ingo