From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755198AbaEJJKX (ORCPT ); Sat, 10 May 2014 05:10:23 -0400 Received: from top.free-electrons.com ([176.31.233.9]:50045 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754608AbaEJJKU (ORCPT ); Sat, 10 May 2014 05:10:20 -0400 Date: Sat, 10 May 2014 11:10:18 +0200 From: Alexandre Belloni To: Nicolas Ferre Cc: linux-arm-kernel@lists.infradead.org, Boris BREZILLON , Jean-Christophe PLAGNIOL-VILLARD , linux-kernel@vger.kernel.org, Bo Shen Subject: Re: [PATCH 1/2] ARM: at91: add PWM pinctrl to SAMA5D3 Message-ID: <20140510091017.GA22329@piout.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Nicolas, On 09/05/2014 at 15:44:27 +0200, Nicolas Ferre wrote : > Signed-off-by: Nicolas Ferre > --- > arch/arm/boot/dts/sama5d3.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi > index 9caa06b3641e..ed7943745f23 100644 > --- a/arch/arm/boot/dts/sama5d3.dtsi > +++ b/arch/arm/boot/dts/sama5d3.dtsi > @@ -583,6 +583,88 @@ > }; > }; > > + pwm0 { > + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { > + atmel,pins = > + ; /* PA20 periph B, conflicts with ISI_D4 and LCDDAT20 */ Didn't we decide at some point to stop adding comments for the pinctrl ? At least, I would say that "PA20 periph B" doesn't add any useful information. > + }; > + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { > + atmel,pins = > + ; /* PB0 periph B, conflicts with GTX0 */ > + }; > + > + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { > + atmel,pins = > + ; /* PA22 periph B, conflicts with ISI_D6 and LCDDAT22 */ > + }; > + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { > + atmel,pins = > + ; /* PB4 periph B, conflicts with GRX0 */ > + }; > + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { > + atmel,pins = > + ; /* PB27 periph C, conflicts with G125CKO and RTS1 */ > + }; > + > + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { > + atmel,pins = > + ; /* PB8 periph B, conflicts with GTXCK */ > + }; > + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { > + atmel,pins = > + ; /* PD5 periph C, conflicts with MCI0_DA4 and TIOA0 */ > + }; > + > + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { > + atmel,pins = > + ; /* PB12 periph B, conflicts with GRXDV */ > + }; > + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { > + atmel,pins = > + ; /* PD7 periph C, conflicts with MCI0_DA6 and TCLK0 */ > + }; > + > + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { > + atmel,pins = > + ; /* PA21 periph B, conflicts with ISI_D5 and LCDDAT21 */ > + }; > + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { > + atmel,pins = > + ; /* PB1 periph B, conflicts with GTX1 */ > + }; I would group pwm0_pwmhx and pwm0_pwmlx together. > + > + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { > + atmel,pins = > + ; /* PA23 periph B, conflicts with ISI_D7 and LCDDAT23 */ > + }; > + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { > + atmel,pins = > + ; /* PB5 periph B, conflicts with GRX1 */ > + }; > + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { > + atmel,pins = > + ; /* PE31 periph B, conflicts with IRQ */ > + }; > + -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com