* [PATCH] perf/x86: fix Haswell precise store data source encoding
@ 2014-05-15 11:53 Stephane Eranian
2014-05-15 14:32 ` Andi Kleen
0 siblings, 1 reply; 3+ messages in thread
From: Stephane Eranian @ 2014-05-15 11:53 UTC (permalink / raw)
To: linux-kernel; +Cc: peterz, mingo, ak, acme, jolsa, jmario, dzickus
This patches fixes a bug in precise_store_data_hsw() whereby
it would set the data source memory level to the wrong value.
As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
Address Information in PEBS Record), when status bit 0 is set
this is a L1 hit, otherwise this is a L1 miss.
This patch encodes the memory level according to the specification.
Signed-off-by: Stephane Eranian <eranian@google.com>
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index ae96cfa..81424f6 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -114,9 +114,13 @@ static u64 precise_store_data_hsw(u64 status)
dse.val = 0;
dse.mem_op = PERF_MEM_OP_STORE;
- dse.mem_lvl = PERF_MEM_LVL_NA;
+ dse.mem_lvl = PERF_MEM_LVL_L1;
+
if (status & 1)
- dse.mem_lvl = PERF_MEM_LVL_L1;
+ dse.mem_lvl |= PERF_MEM_LVL_HIT;
+ else
+ dse.mem_lvl |= PERF_MEM_LVL_MISS;
+
/* Nothing else supported. Sorry. */
return dse.val;
}
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86: fix Haswell precise store data source encoding
2014-05-15 11:53 [PATCH] perf/x86: fix Haswell precise store data source encoding Stephane Eranian
@ 2014-05-15 14:32 ` Andi Kleen
2014-05-15 14:43 ` Stephane Eranian
0 siblings, 1 reply; 3+ messages in thread
From: Andi Kleen @ 2014-05-15 14:32 UTC (permalink / raw)
To: Stephane Eranian
Cc: linux-kernel, peterz, mingo, acme, jolsa, jmario, dzickus
On Thu, May 15, 2014 at 01:53:37PM +0200, Stephane Eranian wrote:
>
> This patches fixes a bug in precise_store_data_hsw() whereby
> it would set the data source memory level to the wrong value.
>
> As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
> Address Information in PEBS Record), when status bit 0 is set
> this is a L1 hit, otherwise this is a L1 miss.
>
> This patch encodes the memory level according to the specification.
It's not enough. as I said it needs more fixes.
For most events it should be _NA, _STORE can be only specified
for the explicit _STORE events.
-Andi
>
> Signed-off-by: Stephane Eranian <eranian@google.com>
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> index ae96cfa..81424f6 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> @@ -114,9 +114,13 @@ static u64 precise_store_data_hsw(u64 status)
>
> dse.val = 0;
> dse.mem_op = PERF_MEM_OP_STORE;
> - dse.mem_lvl = PERF_MEM_LVL_NA;
> + dse.mem_lvl = PERF_MEM_LVL_L1;
> +
> if (status & 1)
> - dse.mem_lvl = PERF_MEM_LVL_L1;
> + dse.mem_lvl |= PERF_MEM_LVL_HIT;
> + else
> + dse.mem_lvl |= PERF_MEM_LVL_MISS;
> +
> /* Nothing else supported. Sorry. */
> return dse.val;
> }
--
ak@linux.intel.com -- Speaking for myself only
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86: fix Haswell precise store data source encoding
2014-05-15 14:32 ` Andi Kleen
@ 2014-05-15 14:43 ` Stephane Eranian
0 siblings, 0 replies; 3+ messages in thread
From: Stephane Eranian @ 2014-05-15 14:43 UTC (permalink / raw)
To: Andi Kleen
Cc: LKML, Peter Zijlstra, mingo@elte.hu, Arnaldo Carvalho de Melo,
Jiri Olsa, Joe Mario, Don Zickus
On Thu, May 15, 2014 at 4:32 PM, Andi Kleen <ak@linux.intel.com> wrote:
> On Thu, May 15, 2014 at 01:53:37PM +0200, Stephane Eranian wrote:
>>
>> This patches fixes a bug in precise_store_data_hsw() whereby
>> it would set the data source memory level to the wrong value.
>>
>> As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
>> Address Information in PEBS Record), when status bit 0 is set
>> this is a L1 hit, otherwise this is a L1 miss.
>>
>> This patch encodes the memory level according to the specification.
>
> It's not enough. as I said it needs more fixes.
>
> For most events it should be _NA, _STORE can be only specified
> for the explicit _STORE events.
>
Yes, I forgot about that. Will re-spin the patch.
> -Andi
>
>>
>> Signed-off-by: Stephane Eranian <eranian@google.com>
>>
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
>> index ae96cfa..81424f6 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
>> @@ -114,9 +114,13 @@ static u64 precise_store_data_hsw(u64 status)
>>
>> dse.val = 0;
>> dse.mem_op = PERF_MEM_OP_STORE;
>> - dse.mem_lvl = PERF_MEM_LVL_NA;
>> + dse.mem_lvl = PERF_MEM_LVL_L1;
>> +
>> if (status & 1)
>> - dse.mem_lvl = PERF_MEM_LVL_L1;
>> + dse.mem_lvl |= PERF_MEM_LVL_HIT;
>> + else
>> + dse.mem_lvl |= PERF_MEM_LVL_MISS;
>> +
>> /* Nothing else supported. Sorry. */
>> return dse.val;
>> }
>
> --
> ak@linux.intel.com -- Speaking for myself only
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-05-15 11:53 [PATCH] perf/x86: fix Haswell precise store data source encoding Stephane Eranian
2014-05-15 14:32 ` Andi Kleen
2014-05-15 14:43 ` Stephane Eranian
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