From: Don Zickus <dzickus@redhat.com>
To: Jiri Olsa <jolsa@redhat.com>
Cc: acme@ghostprotocols.net, peterz@infradead.org,
LKML <linux-kernel@vger.kernel.org>,
namhyung@gmail.com, eranian@google.com,
Andi Kleen <andi@firstfloor.org>
Subject: Re: [PATCH 6/6] perf: Add dcacheline sort
Date: Fri, 16 May 2014 09:30:58 -0400 [thread overview]
Message-ID: <20140516133058.GN50500@redhat.com> (raw)
In-Reply-To: <20140516114757.GD19475@krava.brq.redhat.com>
On Fri, May 16, 2014 at 01:47:57PM +0200, Jiri Olsa wrote:
> On Tue, May 13, 2014 at 12:48:17PM -0400, Don Zickus wrote:
> > In perf's 'mem-mode', one can get access to a whole bunch of details specific to a
> > particular sample instruction. A bunch of those details relate to the data
> > address.
> >
> > One interesting thing you can do with data addresses is to convert them into a unique
> > cacheline they belong too. Organizing these data cachelines into similar groups and sorting
> > them can reveal cache contention.
> >
> > This patch creates an alogorithm based on various sample details that can help group
> > entries together into data cachelines and allows 'perf report' to sort on it.
> >
> > The algorithm relies on having proper mmap2 support in the kernel to help determine
> > if the memory map the data address belongs to is private to a pid or globally shared.
> >
> > The alogortithm is as follows:
> >
> > o group cpumodes together
> > o group entries with discovered maps together
> > o sort on major, minor, inode and inode generation numbers
> > o if userspace anon, then sort on pid
> > o sort on cachelines based on data addresses
>
> needs some collumn width refresh or something..? ;-)
Not sure what you mean here.
>
> # Overhead Data Cacheline
> # ........ .......................
> #
> 5.42% [k] 0xffff8801ed832c40
> 5.29% [.] sys_errlist@@GLIBC_2.12+0xffffffcbf7dfc1ff
> 3.16% [k] 0xffffffffff5690c0
>
>
> also I've got again perf hanged up on opening device file
>
> [jolsa@krava perf]$ sudo strace -p 29445
> Process 29445 attached
> open("/dev/snd/pcmC0D0p", O_RDONLY^CProcess 29445 detached
>
> another one I recall was /dev/dri/card0 touched by X server
>
> I guess those device files allow to mmap memory and we recorded
> memory access there.. we need check for this and do not try to
> open device files
Ok. And that problem doesn't happen when my patch is not applied? I am
not sure how this patch causes open device hangs. I'll try to run this on
a box with X server running to duplicate.
Cheers,
Don
next prev parent reply other threads:[~2014-05-16 13:31 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-13 16:48 [PATCH 0/6 V2] perf: Enable mmap2 and add dcacheline sorting Don Zickus
2014-05-13 16:48 ` [PATCH 1/6] events, perf: Pass protection and flags bits through mmap2 interface Don Zickus
2014-05-16 12:22 ` Peter Zijlstra
2014-05-16 13:33 ` Don Zickus
2014-05-16 15:45 ` Peter Zijlstra
2014-05-16 16:20 ` Don Zickus
2014-05-13 16:48 ` [PATCH 2/6] Revert "perf: Disable PERF_RECORD_MMAP2 support" Don Zickus
2014-05-16 11:25 ` Jiri Olsa
2014-05-16 13:26 ` Don Zickus
2014-05-19 11:45 ` Jiri Olsa
2014-05-19 11:21 ` Jiri Olsa
2014-05-13 16:48 ` [PATCH 3/6] perf: Update mmap2 interface with protection and flag bits Don Zickus
2014-05-13 16:48 ` [PATCH 4/6] perf report: Add mem-mode documentation to report command Don Zickus
2014-05-13 16:48 ` [PATCH 5/6] perf: Add cpumode to struct hist_entry Don Zickus
2014-05-13 16:48 ` [PATCH 6/6] perf: Add dcacheline sort Don Zickus
2014-05-16 11:47 ` Jiri Olsa
2014-05-16 13:30 ` Don Zickus [this message]
2014-05-16 14:05 ` Jiri Olsa
2014-05-16 14:30 ` Don Zickus
2014-05-19 13:34 ` Jiri Olsa
2014-05-19 14:18 ` Don Zickus
2014-05-16 14:09 ` Stephane Eranian
2014-05-16 15:18 ` Don Zickus
2014-05-16 15:59 ` Peter Zijlstra
2014-05-16 16:02 ` Stephane Eranian
2014-05-16 16:24 ` Don Zickus
2014-05-16 16:27 ` Stephane Eranian
2014-05-19 11:25 ` Jiri Olsa
2014-05-19 13:20 ` Don Zickus
2014-05-13 16:52 ` [PATCH 0/6 V2] perf: Enable mmap2 and add dcacheline sorting Don Zickus
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