From: Andi Kleen <ak@linux.intel.com>
To: Stephane Eranian <eranian@google.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
"mingo@elte.hu" <mingo@elte.hu>,
Dave Hansen <dave.hansen@intel.com>,
"Yan, Zheng" <zheng.z.yan@intel.com>
Subject: Re: [RFC] perf/x86: PMU IRQ handler issues
Date: Wed, 28 May 2014 12:55:28 -0700 [thread overview]
Message-ID: <20140528195528.GQ29957@tassilo.jf.intel.com> (raw)
In-Reply-To: <CABPqkBTsiwicZNuU5BW6FZfB4aC=T=w9vFoxLqBTV3-PS4BnoA@mail.gmail.com>
> Another explanation is that because we ACK the NMI early, we leave the
> door open to other interrupts, incl. NIC, and we are interrupting the execution
PMI executes with interrupts off.
> of the PMU IRQ handler, yet that detour is measured in the PMU handler
> latency, causing more throttling than needed. Is that a plausible scenario too?
> And if so, I think we need to narrow the window for timing errors, by
> acking late
> on all processors and not just HSW.
If you think there's a concrete problem please show an ftrace.
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2014-05-28 19:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-28 19:48 [RFC] perf/x86: PMU IRQ handler issues Stephane Eranian
2014-05-28 19:55 ` Andi Kleen [this message]
2014-05-28 19:56 ` Stephane Eranian
2014-05-28 20:06 ` Andi Kleen
2014-05-28 20:20 ` Dave Hansen
2014-05-29 2:56 ` Andi Kleen
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