From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
"mingo@elte.hu" <mingo@elte.hu>,
"ak@linux.intel.com" <ak@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>,
"Yan, Zheng" <zheng.z.yan@intel.com>,
Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com>
Subject: Re: [PATCH 5/9] perf/x86: implement cross-HT corruption bug workaround
Date: Thu, 5 Jun 2014 16:21:35 +0200 [thread overview]
Message-ID: <20140605142135.GM6758@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <CABPqkBQRDpbkF73sWKXiXJOO0Jbeb9tRTWqScbjNdTG50EN3ug@mail.gmail.com>
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On Thu, Jun 05, 2014 at 04:15:17PM +0200, Stephane Eranian wrote:
> On Thu, Jun 5, 2014 at 4:04 PM, Peter Zijlstra <peterz@infradead.org> wrote:
> > On Wed, Jun 04, 2014 at 11:34:14PM +0200, Stephane Eranian wrote:
> >> +
> >> + /*
> >> + * Modify static constraint with current dynamic
> >> + * state of thread
> >> + *
> >> + * EXCLUSIVE: sibling counter measuring exclusive event
> >> + * SHARED : sibling counter measuring non-exclusive event
> >> + * UNUSED : sibling counter unused
> >> + */
> >> + for_each_set_bit(i, cx->idxmsk, X86_PMC_IDX_MAX) {
> >> + /*
> >> + * exclusive event in sibling counter
> >> + * our corresponding counter cannot be used
> >> + * regardless of our event
> >> + */
> >> + if (xl->state[i] == INTEL_EXCL_EXCLUSIVE)
> >> + __clear_bit(i, cx->idxmsk);
> >> + /*
> >> + * if measuring an exclusive event, sibling
> >> + * measuring non-exclusive, then counter cannot
> >> + * be used
> >> + */
> >> + if (is_excl && xl->state[i] == INTEL_EXCL_SHARED)
> >> + __clear_bit(i, cx->idxmsk);
> >> + }
> >> +
> >> + /*
> >> + * recompute actual bit weight for scheduling algorithm
> >> + */
> >> + cx->weight = hweight64(cx->idxmsk64);
> >
> > So I think we talked about this a bit; what happens if CPU0 (taking your
> > 4 core HSW-client) is first to program its counters and takes all 4 in
> > exclusive mode?
> >
> > Then there's none left for CPU4.
> >
> > Did I miss where we avoid that problem, or is that an actual issue?
>
> Yes, this patch series does not address this problem yet. It will be
> in a second series.
> Don't have a good solution yet.
We could limit each cpu to num_counters/2 exclusive slots. That'll still
be painful with some constrained events I imagine, but in general that
should 'work' I suppose.
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next prev parent reply other threads:[~2014-06-05 14:21 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-04 21:34 [PATCH 0/9] perf/x86: implement HT counter corruption workaround Stephane Eranian
2014-06-04 21:34 ` [PATCH 1/9] perf,x86: rename er_flags to flags Stephane Eranian
2014-06-04 21:34 ` [PATCH 2/9] pref/x86: vectorize cpuc->kfree_on_online Stephane Eranian
2014-06-04 21:34 ` [PATCH 3/9] perf/x86: add 3 new scheduling callbacks Stephane Eranian
2014-06-04 21:34 ` [PATCH 4/9] perf/x86: add cross-HT counter exclusion infrastructure Stephane Eranian
2014-06-05 7:47 ` Peter Zijlstra
2014-06-05 10:51 ` Stephane Eranian
2014-06-05 8:04 ` Peter Zijlstra
2014-06-05 13:36 ` Maria Dimakopoulou
2014-06-05 8:29 ` Peter Zijlstra
2014-06-05 21:33 ` Andi Kleen
2014-06-05 21:38 ` Stephane Eranian
2014-06-10 11:53 ` Stephane Eranian
2014-06-10 12:26 ` Peter Zijlstra
2014-06-04 21:34 ` [PATCH 5/9] perf/x86: implement cross-HT corruption bug workaround Stephane Eranian
2014-06-05 13:38 ` Peter Zijlstra
2014-06-05 13:42 ` Peter Zijlstra
2014-06-05 13:48 ` Peter Zijlstra
2014-06-05 14:01 ` Maria Dimakopoulou
2014-06-05 14:04 ` Borislav Petkov
2014-06-05 14:11 ` Peter Zijlstra
2014-06-05 14:14 ` Peter Zijlstra
2014-06-05 14:24 ` Maria Dimakopoulou
2014-06-05 14:04 ` Peter Zijlstra
2014-06-05 14:15 ` Stephane Eranian
2014-06-05 14:21 ` Peter Zijlstra [this message]
2014-06-05 14:26 ` Stephane Eranian
2014-06-05 14:31 ` Peter Zijlstra
2014-06-05 15:31 ` Stephane Eranian
2014-06-04 21:34 ` [PATCH 6/9] perf/x86: enforce HT bug workaround for SNB/IVB/HSW Stephane Eranian
2014-06-04 21:34 ` [PATCH 7/9] perf/x86: enforce HT bug workaround with PEBS " Stephane Eranian
2014-06-04 21:34 ` [PATCH 8/9] perf/x86: fix intel_get_event_constraints() for dynamic constraints Stephane Eranian
2014-06-04 21:34 ` [PATCH 9/9] perf/x86: add syfs entry to disable HT bug workaround Stephane Eranian
2014-06-05 8:32 ` Matt Fleming
2014-06-05 9:29 ` Stephane Eranian
2014-06-05 10:01 ` Matt Fleming
2014-06-05 10:19 ` Stephane Eranian
2014-06-05 11:16 ` Matt Fleming
2014-06-05 12:02 ` Stephane Eranian
2014-06-05 13:27 ` Borislav Petkov
2014-06-05 13:42 ` Stephane Eranian
2014-06-05 14:03 ` Borislav Petkov
2014-06-05 14:45 ` Maria Dimakopoulou
2014-06-05 15:17 ` Borislav Petkov
2014-06-05 16:39 ` Maria Dimakopoulou
2014-06-05 16:47 ` Stephane Eranian
2014-06-05 16:52 ` Borislav Petkov
2014-06-05 18:00 ` Maria Dimakopoulou
2014-06-05 23:29 ` Andi Kleen
2014-06-06 8:28 ` Matt Fleming
2014-06-05 12:50 ` Peter Zijlstra
2014-06-05 12:55 ` Stephane Eranian
2014-06-05 12:59 ` Peter Zijlstra
2014-06-05 13:16 ` Stephane Eranian
2014-06-05 13:26 ` Peter Zijlstra
2014-06-05 13:19 ` Peter Zijlstra
2014-06-05 13:26 ` Stephane Eranian
2014-06-04 22:28 ` [PATCH 0/9] perf/x86: implement HT counter corruption workaround Andi Kleen
2014-06-05 12:45 ` Stephane Eranian
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