From: Matt Fleming <matt@console-pimps.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>,
acme@kernel.org, mingo@redhat.com, paulus@samba.org,
hpa@zytor.com, tglx@linutronix.de, x86@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf/x86/intel: ignore CondChgd bit to avoid false NMI handling
Date: Wed, 11 Jun 2014 13:05:57 +0100 [thread overview]
Message-ID: <20140611120557.GC26290@console-pimps.org> (raw)
In-Reply-To: <20140611115413.GE3588@twins.programming.kicks-ass.net>
On Wed, 11 Jun, at 01:54:13PM, Peter Zijlstra wrote:
>
> Matt found in the MSR listing for GLOBAL_STATUS:
>
> 63 CondChg: status bits of this register has changed. If CPUID.0AH: EAX[7:0] > 0
>
> Which brings us to a grand total of 3 different names for this bit.
Right, I'm flinging emails around to get this fixed in the SDM, so that
the answer to,
Q: "How many kernel developers does it take to find the definition of
this bit?"
is less than 4.
--
Matt Fleming, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-06-11 12:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-11 7:30 [PATCH] perf/x86/intel: ignore CondChgd bit to avoid false NMI handling HATAYAMA Daisuke
2014-06-11 8:54 ` Peter Zijlstra
2014-06-11 11:54 ` Peter Zijlstra
2014-06-11 12:05 ` Matt Fleming [this message]
2014-06-12 7:00 ` HATAYAMA Daisuke
2014-06-12 7:37 ` Peter Zijlstra
2014-06-16 15:21 ` Don Zickus
2014-06-16 15:38 ` Don Zickus
2014-06-12 6:46 ` HATAYAMA Daisuke
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