From: Andi Kleen <ak@linux.intel.com>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
mingo@elte.hu, jmario@redhat.com, dzickus@redhat.com,
jolsa@redhat.com, acme@redhat.com
Subject: Re: [PATCH 2/2] perf/x86: fix constraints for load latency and precise events
Date: Thu, 19 Jun 2014 13:56:24 -0700 [thread overview]
Message-ID: <20140619205624.GZ8178@tassilo.jf.intel.com> (raw)
In-Reply-To: <1403193509-22393-3-git-send-email-eranian@google.com>
On Thu, Jun 19, 2014 at 05:58:29PM +0200, Stephane Eranian wrote:
> The load latency does not have to be constrained to counter 3
> on any of SNB, IVB, HSW. It operates fine on any PEBS-capable
> counter.
>
> The precise store event for SNB, IVB needs to be on counter 3.
> But on Haswell, precise store is implemented differently and
> the constraint is not needed anymore, so we remove it.
Looks good to me.
-Andi
next prev parent reply other threads:[~2014-06-19 20:56 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 15:58 [PATCH 0/2] perf/x86: improve Intel load latency and precise store event constraints Stephane Eranian
2014-06-19 15:58 ` [PATCH 1/2] perf/x86: update Haswell PEBS " Stephane Eranian
2014-06-19 18:00 ` Andi Kleen
2014-06-19 19:53 ` Stephane Eranian
2014-06-19 20:18 ` Andi Kleen
2014-06-19 20:31 ` Stephane Eranian
2014-06-19 20:40 ` Andi Kleen
2014-06-19 20:45 ` Stephane Eranian
2014-06-20 13:44 ` Stephane Eranian
2014-06-23 7:35 ` Peter Zijlstra
2014-06-23 14:16 ` Andi Kleen
2014-06-23 7:14 ` Peter Zijlstra
2014-06-23 8:06 ` Stephane Eranian
2014-06-23 11:37 ` Peter Zijlstra
2014-06-23 11:51 ` Stephane Eranian
2014-06-23 15:47 ` Andi Kleen
2014-06-23 7:12 ` Peter Zijlstra
2014-06-19 15:58 ` [PATCH 2/2] perf/x86: fix constraints for load latency and precise events Stephane Eranian
2014-06-19 20:56 ` Andi Kleen [this message]
2014-06-23 8:42 ` Peter Zijlstra
2014-06-23 9:00 ` Stephane Eranian
2014-06-23 11:39 ` Peter Zijlstra
2014-06-23 14:22 ` Andi Kleen
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