From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>,
Mike Turquette <mturquette@linaro.org>,
spear-devel@list.st.com, stable@vger.kernel.org
Subject: [patch 1/2] clk: spear3xx: Use proper control register offset
Date: Thu, 19 Jun 2014 21:52:23 -0000 [thread overview]
Message-ID: <20140619215140.259138132@linutronix.de> (raw)
In-Reply-To: 20140619214858.755664030@linutronix.de
[-- Attachment #1: spear-clk-fix-crap.patch --]
[-- Type: text/plain, Size: 877 bytes --]
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
---
drivers/clk/spear/spear3xx_clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux/drivers/clk/spear/spear3xx_clock.c
===================================================================
--- linux.orig/drivers/clk/spear/spear3xx_clock.c
+++ linux/drivers/clk/spear/spear3xx_clock.c
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi
/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
-#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
+#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
#define SPEAR320_UARTX_PCLK_MASK 0x1
next prev parent reply other threads:[~2014-06-19 21:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 21:52 [patch 0/2] clk: spear3xx: Make it actually work Thomas Gleixner
2014-06-19 21:52 ` Thomas Gleixner [this message]
2014-06-20 4:51 ` [patch 1/2] clk: spear3xx: Use proper control register offset Viresh Kumar
2014-06-19 21:52 ` [patch 2/2] clk: spear3xx: Set proper clock parent of uart1/2 Thomas Gleixner
2014-06-20 5:41 ` Viresh Kumar
2014-06-20 7:53 ` Thomas Gleixner
2014-07-13 14:12 ` [patch 0/2] clk: spear3xx: Make it actually work Mike Turquette
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