Re: [PATCH 2/2] perf/x86: fix constraints for load latency and precise events

[Andi Kleen <ak@linux.intel.com>]

> I don't know why they did it this way. I think somehow, it is believe that
> ll and st cannot be captured together (and putting both on cnt3 enforces
> that). But when it seems to be working fine. If someone from Intel can
> confirm this is okay/not okay then we can revisit.

Depending on the CPU, if you have multiple load and store threshold events
active at the same time it may capture junk.

So it's better to keep that constraint too, or enforce it with other 
ways (e.g. an extra reg)

> You can say the same with PREC_DIST which up until HSW needs to be
> taken alone, i.e., no other event active. We don't enforce that either, it would
> cause problems with the NMI watchdog.

I believe it's only sandy bridge where it needs to be taken alone.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only