From: Marek Vasut <marex@denx.de>
To: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Harro Haan <hrhaan@gmail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, patches@linaro.org,
linaro-kernel@lists.linaro.org,
John Stultz <john.stultz@linaro.org>,
Nicolas Pitre <nicolas.pitre@linaro.org>,
Christoffer Dall <christoffer.dall@linaro.org>,
Sricharan R <r.sricharan@ti.com>
Subject: Re: [PATCH RFC 1/9] irqchip: gic: Provide support for interrupt grouping
Date: Mon, 21 Jul 2014 18:07:00 +0200 [thread overview]
Message-ID: <201407211807.00119.marex@denx.de> (raw)
In-Reply-To: <1405954040-30399-2-git-send-email-daniel.thompson@linaro.org>
On Monday, July 21, 2014 at 04:47:12 PM, Daniel Thompson wrote:
> All GIC hardware except GICv1-without-TrustZone support provides a means
> to group exceptions into group 0 (which can optionally be signally using
> use FIQ) and group 1. The kernel currently provides no means to exploit
> this. This patch alters the initialization of the GIC to place all
> interrupts into group 1 which is the foundational requirement to
> meaningfully use FIQ.
[...]
> @@ -670,7 +753,11 @@ static void gic_raise_softirq(const struct cpumask
> *mask, unsigned int irq) dmb(ishst);
>
> /* this always happens on GIC0 */
> - writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) +
> GIC_DIST_SOFTINT); + softint = map << 16 | irq;
> + if (gic_data_fiq_enable(&gic_data[0]))
> + softint |= 0x8000;
These magic bits here could use some clarification, possibly a comment.
> + writel_relaxed(softint,
> + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
>
> raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
> }
[...]
Best regards,
Marek Vasut
next prev parent reply other threads:[~2014-07-21 16:15 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-21 14:47 [PATCH RFC 0/9] Fix INTACK for FIQ support on ARM Cortex A9 Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 1/9] irqchip: gic: Provide support for interrupt grouping Daniel Thompson
2014-07-21 16:07 ` Marek Vasut [this message]
2014-07-21 14:47 ` [PATCH RFC 2/9] irqchip: gic: Add support for FIQ management Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 3/9] irqchip: gic: Remove spin locks from eoi_irq Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 4/9] ARM: dump the status of NS bit in L1 PTE Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 5/9] ARM: Add L1 PTE non-secure mapping Daniel Thompson
2014-07-21 16:46 ` Russell King - ARM Linux
2014-07-22 10:16 ` Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 6/9] arm: mm: Avoid ioremap_page_range() for non-secure mappings Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 7/9] irqchip: gic: Use non-secure aliased register set when FIQ is enabled Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 8/9] ARM: socfpga: Map the GIC CPU registers as MT_DEVICE_NS Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 9/9] arm: imx: non-secure aliased mapping of GIC registers Daniel Thompson
2014-07-21 16:15 ` Marek Vasut
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