From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755251AbaGUWaZ (ORCPT ); Mon, 21 Jul 2014 18:30:25 -0400 Received: from mail.skyhub.de ([78.46.96.112]:34488 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755185AbaGUWaO (ORCPT ); Mon, 21 Jul 2014 18:30:14 -0400 Date: Tue, 22 Jul 2014 00:30:09 +0200 From: Borislav Petkov To: Andy Lutomirski Cc: Peter Zijlstra , Thomas Gleixner , x86-ml , lkml , Steven Rostedt Subject: Re: [PATCH] x86, TSC: Add a software TSC offset Message-ID: <20140721223009.GF11555@pd.tnic> References: <20140719130602.GA5101@pd.tnic> <53CD6B50.5010404@mit.edu> <20140721213534.GB11555@pd.tnic> <20140721215225.GD11555@pd.tnic> <20140721220825.GE11555@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 21, 2014 at 03:13:33PM -0700, Andy Lutomirski wrote: > Ha. Ha ha. Muahaha. Because IIRC this box is synced until the first > time it suspends. Sweet, TSCs get fumbled in some S-state or maybe SMI... Who TF knows. Well, I'm thinking upon resume, we run through smpboot which should do the tsc sync check again. Will have to test to see. > > diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h > > index 94605c0e9cee..ad7d5e449c0b 100644 > > --- a/arch/x86/include/asm/tsc.h > > +++ b/arch/x86/include/asm/tsc.h > > @@ -27,7 +27,9 @@ static inline cycles_t get_cycles(void) > > if (!cpu_has_tsc) > > return 0; > > #endif > > + rdtsc_barrier(); > > rdtscll(ret); > > + rdtsc_barrier(); > > > > Only the first of these is necessary. There was a long thread on this > a couple of years ago, and the conclusion was that the code in > vread_tsc in vclock_gettime.c is correct. * The various CPU manuals are unclear * as to whether rdtsc can be reordered with later loads, * but no one has ever seen it happen. until some future uarch proves you wrong. :-) I guess we can try with one pre-fence only first although if we're doing one already, I can't imagine the post-one to be all that expensive since we've retired the whole inflight crap already anyway. -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. --