Re: Power Scheduler Design

Alex Shi
2014-09-07T14:29:40Z

于 9/7/14, 4:47, Abel Vesa 写道:
> For a while now, I've started studying the power aware scheduling problem.
> And like many other rookies out there I took all the lkml mails related
> and read them all (well, almost all) and I saw that there are some
> debating on the implementation.I even look over the implementation
> proposed of Preeti U Murthy. I also worked (just for fun) for a while on
> some ideas of my own (nothing worth sharing, yet) but I have problem
> understanding the design requirements. Here is one.
>
> Some of you (even Ingo) said that the scheduler should be the one to
> manage the cpu P/C states. In this case the governors of the cpuidle and
> cpufreq would not make any sense anymore. Does that mean they will not
> be a part of this scheduling solution anymore?
CPUIDLE and CPUFREQ are used for cpu power saving when related CPU is
not busy.
Scheduling is coordinate the system load and cpu load. Currently.
Scheduling has no much
idea of CPUIDLE/CPUFREQ status, then may give task to a cpu which in
poor latency or poor
powersaving status. That leads to poor latency and high cost of power.

The power aware scheduling target is to know and coordinate the
cpuidle/cpufreq in scheduling.
Then tasks will be assigned to a cpu unit with better
latency/powersaving consideration.

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