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From: Marek Vasut <marex@denx.de>
To: "Bean Huo =?utf-8?q?=E9=9C=8D=E6=96=8C=E6=96=8C?= (beanhuo)" 
	<beanhuo@micron.com>
Subject: Re: [PATCH 1/1 v3] driver:mtd:spi-nor: Add Micron quad I/O support
Date: Tue, 30 Sep 2014 15:38:40 +0200
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Cc: "dwmw2@infradead.org" <dwmw2@infradead.org>,
        Brian Norris <computersforpeace@gmail.com>,
        "shijie8@gmail.com" <shijie8@gmail.com>,
        "geert+renesas@glider.be" <geert+renesas@glider.be>,
        "grmoore@altera.com" <grmoore@altera.com>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
References: <A765B125120D1346A63912DDE6D8B6315DCC46@NTXXIAMBX02.xacn.micron.com> <201409261046.07132.marex@denx.de> <A765B125120D1346A63912DDE6D8B6315E3C79@NTXXIAMBX02.xacn.micron.com>
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On Tuesday, September 30, 2014 at 04:47:39 AM, Bean Huo 霍斌斌 (beanhuo) wrote:
> For Micron spi norflash,enables or disables quad I/O
> protocol ,which controled by EVCR(Enhanced
> Volatile Configuration Register) Quad I/O
> protocol bit 7.When EVCR bit 7 is reset to 0,
> the spi norflash will operate in quad I/O following
> the next WRITE ENHANCED VOLATILE CONFIGURATION
> command.

You only do one WRITE ENHANCED VOLATILE CONFIGURATION command in the patch, so
this text doesn't add up.

Try something like this:
-->8--
This patch adds code which enables Quad I/O mode on Micron SPI NOR
flashes.

For Micron SPI NOR flash, enabling or disabling quad I/O protocol
is controled by EVCR (Enhanced Volatile Configuration Register),
Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI
NOR flash will operate in quad I/O mode.
--8<--

What do you think ?

Brian, am I bitching too much about pointless things ? Please stop me if you 
think I do.

[...]

Best regards,
Marek Vasut