From: Peter Zijlstra <peterz@infradead.org>
To: Vikas Shivappa <vikas.shivappa@intel.com>
Cc: Tejun Heo <tj@kernel.org>, "Auld, Will" <will.auld@intel.com>,
Matt Fleming <matt@console-pimps.org>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Fleming, Matt" <matt.fleming@intel.com>,
h.peter.anvin@intel.com
Subject: Re: Cache Allocation Technology Design
Date: Tue, 4 Nov 2014 14:17:14 +0100 [thread overview]
Message-ID: <20141104131714.GR3219@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <alpine.DEB.2.10.1410301610000.27874@vshiva-Udesk>
On Thu, Oct 30, 2014 at 04:18:33PM -0700, Vikas Shivappa wrote:
> One way to it is to merge the CAT cgroups into the cpuset . In essense there
> is no CAT cgroup seperately and we just have a new file 'cbm' in the cpuset.
> This would be visible only when system has Cache allocation support and the
> user can manipulate the cache bit mask here.
> The user can use the already existing cpu_exclusive file in the cpuset to
> mark the cgroups to use exclusive CPUs.
> That way we simplify and reuse cpuset code/hierarchy .. ?
I don't like extending cpusets further. Its already a weird and too big
controller.
What is wrong with having a specific CQM controller and using it
together with cpusets where desired?
next prev parent reply other threads:[~2014-11-04 13:17 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-16 18:44 Cache Allocation Technology Design vikas
2014-10-20 16:18 ` Matt Fleming
2014-10-24 10:53 ` Peter Zijlstra
2014-10-28 23:22 ` Matt Fleming
2014-10-29 8:16 ` Peter Zijlstra
2014-10-29 12:48 ` Matt Fleming
2014-10-29 13:45 ` Peter Zijlstra
2014-10-29 16:32 ` Auld, Will
2014-10-29 17:28 ` Peter Zijlstra
2014-10-29 17:41 ` Vikas Shivappa
2014-10-29 18:22 ` Tejun Heo
2014-10-30 7:07 ` Peter Zijlstra
2014-10-30 7:14 ` Peter Zijlstra
2014-10-30 12:44 ` Tejun Heo
2014-10-30 13:19 ` Peter Zijlstra
2014-10-30 15:25 ` Tejun Heo
2014-10-30 12:43 ` Tejun Heo
2014-10-30 13:18 ` Peter Zijlstra
2014-10-30 17:03 ` Tejun Heo
2014-10-30 21:43 ` Peter Zijlstra
2014-10-30 22:22 ` Tejun Heo
2014-10-30 22:47 ` Peter Zijlstra
2014-11-06 16:27 ` Matt Fleming
2014-11-06 17:20 ` Vikas Shivappa
2014-10-31 13:07 ` Peter Zijlstra
2014-10-31 15:58 ` Tejun Heo
2014-11-04 13:13 ` Peter Zijlstra
2014-11-05 20:41 ` Tejun Heo
2014-10-30 14:14 ` Matt Fleming
[not found] ` <CAAAKZwvJOKsrj_yczDGaNLaNYo+_=HzsTLwDdcaTJqO2VMy8uA@mail.gmail.com>
2014-10-30 17:12 ` Tejun Heo
2014-10-30 22:35 ` Tim Hockin
2014-10-31 16:57 ` Tejun Heo
2014-10-30 23:18 ` Vikas Shivappa
2014-11-04 13:17 ` Peter Zijlstra [this message]
2014-11-06 17:03 ` Matt Fleming
2014-11-10 15:50 ` Peter Zijlstra
2014-10-29 17:26 ` Vikas Shivappa
2014-10-29 18:16 ` Peter Zijlstra
2014-11-03 23:29 ` Vikas Shivappa
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