From: Borislav Petkov <bp@alien8.de>
To: Vikas Shivappa <vikas.shivappa@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@kernel.org,
tj@kernel.org, matt.flemming@intel.com, will.auld@intel.com,
peterz@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
Date: Fri, 21 Nov 2014 21:15:20 +0100 [thread overview]
Message-ID: <20141121201520.GA5473@pd.tnic> (raw)
In-Reply-To: <alpine.DEB.2.10.1411211123150.30781@vshiva-Udesk>
On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
> >>+char hsw_brandstrs[5][64] = {
> >>+ "Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz",
> >>+ "Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz",
> >>+ "Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz",
> >>+ "Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz",
> >>+ "Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz"
> >>+};
> >>+
> >>+#define cacheqe_for_each_child(child_cq, pos_css, parent_cq) \
> >>+ css_for_each_child((pos_css), \
> >>+ &(parent_cq)->css)
> >>+
> >>+#if CONFIG_CACHEQE_DEBUG
> >
> >We really do NOT need another config option for this. See above.
> >
> >>+/*DUMP the closid-cbm map.*/
> >
> >Wow that comment is really informative.
> >
> >>+static inline bool cqe_enabled(struct cpuinfo_x86 *c)
> >>+{
> >>+
> >>+ int i;
> >>+
> >>+ if (cpu_has(c, X86_FEATURE_CQE_L3))
> >>+ return true;
> >>+
> >>+ /*
> >>+ * Hard code the checks and values for HSW SKUs.
> >>+ * Unfortunately! have to check against only these brand name strings.
> >>+ */
> >
> >You must be kidding.
>
> No. Will have a microcode version check as well in next patch after thats
> confirmed from h/w team
Checking random brand strings? Please don't tell me those are not really
immutable either...
And what happens with newer models appearing? Add more brand strings?
Lovely stuff, that.
Well, since you're talking to the h/w team: can they give you some
immutable bit somewhere which you can check instead of looking at brand
strings? This'll be a sane solution, actually.
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
next prev parent reply other threads:[~2014-11-21 20:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-20 1:05 [PATCH] x86: Intel Cache Allocation Technology support Vikas Shivappa
2014-11-21 14:19 ` Thomas Gleixner
2014-11-21 20:00 ` Vikas Shivappa
2014-11-21 20:15 ` Borislav Petkov [this message]
2014-11-21 21:14 ` Vikas Shivappa
2014-11-23 20:04 ` Thomas Gleixner
2014-11-24 9:36 ` Shivappa, Vikas
2014-11-23 19:26 ` Matt Fleming
2014-11-23 19:29 ` Thomas Gleixner
2014-11-24 9:44 ` Shivappa, Vikas
2014-11-26 0:01 ` Shivappa, Vikas
2014-11-26 0:05 ` Shivappa, Vikas
2014-11-21 20:29 ` Dave Hansen
2014-11-21 20:43 ` Thomas Gleixner
2014-11-21 21:27 ` Vikas Shivappa
2014-11-21 21:25 ` Vikas Shivappa
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20141121201520.GA5473@pd.tnic \
--to=bp@alien8.de \
--cc=hpa@zytor.com \
--cc=linux-kernel@vger.kernel.org \
--cc=matt.flemming@intel.com \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
--cc=tglx@linutronix.de \
--cc=tj@kernel.org \
--cc=vikas.shivappa@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=will.auld@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox