Re: Question about patch "i2c: omap: resize fifos before each message"

[Felipe Balbi <balbi@ti.com>]

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Hi,

On Wed, Dec 03, 2014 at 06:11:18PM +0300, Alexander Kochetkov wrote:
> Felipe,
> 
> Question about the patch[1].
> 
> I want to change the code in a way to not touch fifo thresholds for
> each message.  Because:
>
> 1. dev->threshold is valid only with checking of transfer direction.
> So, if last transfer was transmission and ISR get RRDY interrupt from
> slave receiver, then dev->threshold is invalid. We must read threshold
> value from BUF register, to process correctly.

What I noticed, however, is that threshold value from BUF wasn't very
reliable. My memory is now really fuzzy, but when I talked to the person
who maintained this IP RTL inside TI, there were some "interesting"
requirements wrt when BUF's threshold was valid and I had a hard time
ensuring that access time.

> 2. I want to avoid changing fifos before message submission, because
> IP can start receiving message in a slave mode (race).

I2C is not full-duplex. There's no way it will receive any data while
you're transmitting, right ?

> 3. dev->threshold is changed in range 1-fifo_size/2. So instead of RDR
> we get RRDY and for messages larger then fifo_size/2 we still get RRDY
> and RDR.

we will only get RDR if message_size % threshold > 0. If we have a 16
byte transfer and we program threshold to 8 bytes, we will get two RRDY
IRQs.

> Felipe, do you have in mind why do you want to avoid RDR and XDR events?
> Something about errata?

nothing about errata. As the commit log say (or tried to say), if the
entire message fits into the FIFO we save one interrupt. It's a
micro-optimization.

> [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-omap.c?id=dd74548ddece4b9d68e5528287a272fa552c81d0

-- 
balbi

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