From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753172AbbAGOzs (ORCPT ); Wed, 7 Jan 2015 09:55:48 -0500 Received: from mail-we0-f178.google.com ([74.125.82.178]:41777 "EHLO mail-we0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752139AbbAGOzq (ORCPT ); Wed, 7 Jan 2015 09:55:46 -0500 X-Greylist: delayed 454 seconds by postgrey-1.27 at vger.kernel.org; Wed, 07 Jan 2015 09:55:45 EST Date: Wed, 7 Jan 2015 15:48:08 +0100 From: Thierry Reding To: Vince Hsu Cc: Peter De Schrijver , Lucas Stach , swarren@wwwdotorg.org, gnurou@gmail.com, bskeggs@redhat.com, martin.peres@free.fr, seven@nimrod-online.com, samuel.pitoiset@gmail.com, nouveau@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/11] ARM: tegra: add function to control the GPU rail clamp Message-ID: <20150107144805.GF1621@ulmo> References: <1419331204-26679-1-git-send-email-vinceh@nvidia.com> <1419331204-26679-2-git-send-email-vinceh@nvidia.com> <1419426990.2179.7.camel@lynxeye.de> <549B7638.2010405@nvidia.com> <20150105150932.GG12010@ulmo.nvidia.com> <20150107101900.GP10073@tbergstrom-lnx.Nvidia.com> <54AD0F37.5080609@nvidia.com> <20150107132709.GA6988@ulmo> <20150107140852.GR10073@tbergstrom-lnx.Nvidia.com> <20150107142828.GB7392@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="/QKKmeG/X/bPShih" Content-Disposition: inline In-Reply-To: <20150107142828.GB7392@nvidia.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --/QKKmeG/X/bPShih Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 07, 2015 at 10:28:29PM +0800, Vince Hsu wrote: > On 04:08:52PM Jan 07, Peter De Schrijver wrote: > > On Wed, Jan 07, 2015 at 02:27:10PM +0100, Thierry Reding wrote: > >=20 > > > > Yeah. I plan to have the information of all the clock client of the > > > > partitions and > > > > the memory clients be defined statically in c source, e.g. pmc-tegr= a124.c. > > > > All modules can declare which domain they belong to in DT. One doma= in can > > > > be really power gated only when no module is awake. Note the clock = clients > > > > of > > > > one domain might not equal to the clocks of the module. The reset i= s not > > > > either. > > > > So I don't get the clock and reset from module. How do you think? > > >=20 > > > This whole situation is quite messy. The above sequence basically mea= ns > > > that drivers can't reset hardware modules because otherwise they might > > > race with the power domain code. It also means that we can't powergate > >=20 > > The powerdomain framework won't call any powergating method as long as a > > module in the domain is still active. So as long as drivers don't try to > > reset the hw without having done a pm_runtime_get(), we shouldn't have = such > > a race? > Agree. And as long as the driver has the correct reset procedure, that sh= ould > be fine to occur between power ungating and gating sequences. >=20 > >=20 > > > modules on demand because they might be in the same power domain as o= ne > > > other module that's still busy. > > >=20 > >=20 > > The powerdomain framework keeps track of which modules are active (by h= ooking > > into runtime pm) and won't try to shutdown a domain unless all modules = are > > inactive. > Yeah. By the way, that means we should start supporting runtime pm for all > the modules to use generic power domain. Indeed, that'll be a prerequisite before we can merge power domain support. I do have a couple of local patches that add very rudimentary runtime PM for various drivers. For starters we could probably just do the pm_runtime_enable(...); pm_runtime_get_sync(...) in the ->probe() and pm_runtime_put_sync(...); pm_runtime_disable(...); in the ->remove() callbacks for those drivers. That's by no means optimal but should get us pretty close to what we do now and still support the generic power domains. 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