From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757955AbbAIQby (ORCPT ); Fri, 9 Jan 2015 11:31:54 -0500 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:56329 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752563AbbAIQbw (ORCPT ); Fri, 9 Jan 2015 11:31:52 -0500 Date: Fri, 9 Jan 2015 17:31:49 +0100 From: Pavel Machek To: Vlastimil Babka Cc: One Thousand Gnomes , Andy Lutomirski , "Kirill A. Shutemov" , Mark Seaborn , kernel list Subject: Re: DRAM unreliable under specific access patern Message-ID: <20150109163149.GA18076@amd> References: <20141224220818.GA17655@amd> <20150105192329.5f32c155@lxorguk.ukuu.org.uk> <20150106014718.GA23775@node.dhcp.inet.fi> <20150106021836.GA24121@node.dhcp.inet.fi> <20150108130325.0592b18b@lxorguk.ukuu.org.uk> <54AFF8B5.8050305@suse.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <54AFF8B5.8050305@suse.cz> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi! > Then it's also quite trivial to induce cache misses without clflush, using just > few addresses that map to the same cache set, without having to cycle throuh > more memory than the cache size is. Hmm. If you can do "clflush" without "clflush", and result is no more then 10 times slower than "clflush", you can probably break it. Might need two DIMMs so that you can use one to flush caches while row-hammering the other one. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html