Re: [PATCH 1/2] watchdog: dw_wdt: pat the watchdog before enabling it

[Jisheng Zhang <jszhang@marvell.com>]

Dear Doug,

On Wed, 21 Jan 2015 15:17:22 -0800
Doug Anderson <dianders@chromium.org> wrote:

> On some dw_wdt implementations the "top" register may be initted to 0
> at bootup.  In such a case, each "pat" of the watchdog will reset the
> timer to 0xffff.  That's pretty short.

+ Guenter Roeck

This should have been fixed by dfa07141e7a792("watchdog: dw_wdt: initialise
TOP_INIT in dw_wdt_set_top()")

In fact, my original fix is as similar as your patch

http://www.spinics.net/lists/arm-kernel/msg363658.html

Then Guenter Roeck suggest one elegant solution which is the base of
commit dfa07141e7a792.

http://www.spinics.net/lists/arm-kernel/msg363908.html

> 
> The input clock of the wdt can be any of a wide range of values.  On
> an rk3288 system, I've seen the wdt clock be 24.75 MHz.  That means
> each tick is ~40ns and we'll count to 0xffff in ~2.6ms.
> 
> Because of the above two facts, it's a really good idea to pat the
> watchdog after initting the "top" register properly and before
> enabling the watchdog.  If you don't then there's no way we'll get the
> next heartbeat in time.
> 
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> ---
>  drivers/watchdog/dw_wdt.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
> index b34a2e4..fc92bea 100644
> --- a/drivers/watchdog/dw_wdt.c
> +++ b/drivers/watchdog/dw_wdt.c
> @@ -170,6 +170,7 @@ static int dw_wdt_open(struct inode *inode, struct file
> *filp)
>  		 * the maximum and then start it.
>  		 */
>  		dw_wdt_set_top(DW_WDT_MAX_TOP);
> +		dw_wdt_keepalive();
>  		writel(WDOG_CONTROL_REG_WDT_EN_MASK,
>  		       dw_wdt.regs + WDOG_CONTROL_REG_OFFSET);
>  	}