Re: [PATCH V2] x86, mce, amd: Enable interrupts by default if HW capable

[Borislav Petkov <bp@alien8.de>]

On Mon, Feb 02, 2015 at 11:02:41AM -0600, Aravind Gopalakrishnan wrote:
> We setup APIC vectors for threshold errors if interrupt_capable.
> However, we don't set interrupt_enable by default.
> Re-working threshold_restart_bank() here so that the first time we
> set up lvt_offset, we also set IntType to APIC.
> 
> User is still allowed to disable interrupts through sysfs.
> 
> While at it, check if status is valid before we proceed to log
> error using mce_log. This is because, in multi-node platforms,
> only NBC has valid status info. So, the decoding of status values
> on the non-NBC leads to noise on kernel logs like so-
> 
> [  440.509744] EDAC DEBUG: amd64_inject_write_store: section=0x80000000
> word_bits=0x10020001
> [  466.570925] [Hardware Error]: Corrected error, no action required.
> [  466.570935] [Hardware Error]: CPU:25 (15:2:0) MC4_STATUS[-|CE|-|-|-
> [  466.570936] [Hardware Error]: Corrected error, no action required.
> [  466.570959] [Hardware Error]: CPU:26 (15:2:0) MC4_STATUS[-|CE|-|-|-
> <...>
> [  466.571293] WARNING: CPU: 25 PID: 0 at drivers/edac/amd64_edac.c:2147
> decode_bus_error+0x1ba/0x2a0()
> [  466.571301] WARNING: CPU: 26 PID: 0 at drivers/edac/amd64_edac.c:2147
> decode_bus_error+0x1ba/0x2a0()
> [  466.571303] Something is rotten in the state of Denmark.
> 
> Suggested-by: Borislav Petkov <bp@suse.de>
> Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>

Queued for 3.21, thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--