From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756000AbbBGPpH (ORCPT ); Sat, 7 Feb 2015 10:45:07 -0500 Received: from down.free-electrons.com ([37.187.137.238]:46372 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754974AbbBGPpF (ORCPT ); Sat, 7 Feb 2015 10:45:05 -0500 Date: Sat, 7 Feb 2015 16:44:09 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: Rob Herring , Grant Likely , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v4 0/5] ARM: sun9i: Add USB host controller support for A80 Message-ID: <20150207154409.GS2079@lukather> References: <1422915725-26492-1-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="R0KbGFzrRdaLlFh/" Content-Disposition: inline In-Reply-To: <1422915725-26492-1-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --R0KbGFzrRdaLlFh/ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 03, 2015 at 06:22:00AM +0800, Chen-Yu Tsai wrote: > Hi everyone, >=20 > This is v4 of the sun9i A80 USB host support series. >=20 > Changes since v3: >=20 > - Dropped patches merged. >=20 > - Moved reg_usb3_vbus into the optimus board dts >=20 > - Dropped ohci1 from A80 dtsi. >=20 > Cover letter from v3: >=20 > This series adds USB host controller (EHCI/OHCI) support for the Allwinner > A80 SoC. The A80 has 3 pairs of host controllers and USB PHYs. The PHYs, > unlike in previous SoCs, do not have low level control registers anymore. >=20 > As such, this series forgoes the original phy-sun4i-usb driver, and adds > a new, simpler driver for the USB PHYs. It may be possible to merge the > two, but given that work is being done on the OTG front for the earlier > SoCs, it may be better to merge them after support is complete. >=20 > EHCI/OHCI0 corresponds to USB1 DP/DM pins; EHCI1 only has HSIC support; > EHCI2/OHCI/2 is USB2 DP/DM externally. External pins labeled USB0 are > for the USB 3.0 OTG controller. Applied 2-5. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --R0KbGFzrRdaLlFh/ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJU1jLJAAoJEBx+YmzsjxAguscP/R0bzuj94+o5xAG9tWKr3swd 1Qwv9FnPMMKJuS2s4pzPnwcXlrfjanIpZ40QvCNSVs4byz5alPyBX5gu3e+nMDG8 9BzV3YpEN/4zp29Rn3n5gjLgibdYOCVlWQufBQrXsuNEVR9ccatBgOI5VaPOTLlN 8V/jSYl+Skvi91LwlXuh5nobvW+0QZiDg5sfVeN8/2NY5TLESGuVzSix8bYw9en4 R9b7j3Jdfphueduu7XMQe70eBYdx1Sp+YIeQtBoVFXpsy/36h7VRgd0jtc+TFjOw 82wujuGPUpTP2Ucv52K/dhPumV81a4q7Cs2sX5PG2I1efX6aQcLDmOwBBDf7HEhL 0MpG9aDhdomou5NnrFRSG9UIDvHVA4d5ZKdb+VSlCD1BQHCsMoppYtqa3Gi6uO9M Fy0Md/qdYjpdClusAACyN0bA0gbo7hVaqNmxUXUw+spmtQrAO+x+7TY6+dcxrzpC r4Onb+k1E18w0cpO9zdowzHGDJL6L+hcuAgTXD45So8I9+YimDMOcV2ArLKtqSwu ZLnwOHbFPqHUCnuyA6epgOLGI+n0+BaV1sSTR8FxlL/BrB+QLHHfKPI3VRS9yMza wgQtQqCkdeFvcX5Z66PfLdDF0I8a9HTu1tdGmuPbFrY7fyOh9SjTGg5acU97/p83 PLG3JqCfHwG3Akd+VXPS =NCAo -----END PGP SIGNATURE----- --R0KbGFzrRdaLlFh/--