From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754672AbbB0TIc (ORCPT ); Fri, 27 Feb 2015 14:08:32 -0500 Received: from foss.arm.com ([217.140.101.70]:44023 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752181AbbB0TIb (ORCPT ); Fri, 27 Feb 2015 14:08:31 -0500 Date: Fri, 27 Feb 2015 19:08:03 +0000 From: Mark Rutland To: Pranith Kumar Cc: Catalin Marinas , Steve Capper , Will Deacon , open list , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC PATCH] ARM64: cmpxchg.h: Clear the exclusive access bit on fail Message-ID: <20150227190800.GE9011@leverpostej> References: <1425016026-19766-1-git-send-email-bobby.prani@gmail.com> <20150227100612.GB3628@arm.com> <20150227183301.GL17949@e104818-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 27, 2015 at 06:44:19PM +0000, Pranith Kumar wrote: > On Fri, Feb 27, 2015 at 1:33 PM, Catalin Marinas > wrote: > > It's either badly formatted or I don't get it. Are the "stxr x1" and > > "stxr x7" happening on the same CPU (P0)? If yes, that's badly written > > code, not even architecturally compliant (you are not allowed other > > memory accesses between ldxr and stxr). > > OK. Is that the same case with ldaxr (acquire) and stlxr (release)? > AFAIK, memory accesses between acquire and release exclusive > operations are allowed. The restriction on memory accesses in the middle of a load-exclusive store-exclusive sequence applies to all the load/store-exclusive variants, including ldaxr and stlxr. Thanks, Mark.