Re: [PATCH] ipc/sem.c: Update/correct memory barriers.

[Oleg Nesterov <oleg@redhat.com>]

On 02/28, Paul E. McKenney wrote:
>
> The idea is that this would become a no-op on x86, s390, sparc &c, an isb
> instruction on ARM, an isync instruction on Power, and I cannot remember
> what on Itanium?  The other idea being to provide read-to-read control
> ordering in addition to the current read-to-write control ordering?

To me, the only purpose is documentation. Let's look at task_work_run()

		/*
		 * Synchronize with task_work_cancel(). It can't remove
		 * the first entry == work, cmpxchg(task_works) should
		 * fail, but it can play with *work and other entries.
		 */
		raw_spin_unlock_wait(&task->pi_lock);
		smp_mb();

It doesn't need the full mb() too. But rmb() will look very confusing
without a fat comment. So I think that it would be nice to write this
comment once and put it into the new helper.

Oleg.