* [PATCH] pwm: mxs: fix period divider computation
@ 2015-02-18 13:06 Gaetan Hug
2015-03-02 12:32 ` Shawn Guo
0 siblings, 1 reply; 3+ messages in thread
From: Gaetan Hug @ 2015-02-18 13:06 UTC (permalink / raw)
To: thierry.reding
Cc: linux-pwm, linux-kernel, shawn.guo, fabio.estevam, Gaetan Hug
The driver computes which clock divider it sould be using from the
requested period. This computation assumes that the link between the
register value and the actual divider value is raising 2 to the power of
the registry value.
div = 1 << regvalue
This is true only for the first 5 values out of 8. Next values are 64,
256 and, 1024 - instead of 32, 64, 128.
This affects only the users requesting a period > 0.04369s.
Replace the computation with a look-up table.
---
drivers/pwm/pwm-mxs.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c
index f75ecb0..c65e183 100644
--- a/drivers/pwm/pwm-mxs.c
+++ b/drivers/pwm/pwm-mxs.c
@@ -35,6 +35,8 @@
#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
#define PERIOD_CDIV_MAX 8
+static unsigned const int cdiv[PERIOD_CDIV_MAX] = {1, 2, 4, 8, 16, 64, 256, 1024};
+
struct mxs_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
@@ -54,13 +56,13 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
rate = clk_get_rate(mxs->clk);
while (1) {
- c = rate / (1 << div);
+ c = rate / cdiv[div];
c = c * period_ns;
do_div(c, 1000000000);
if (c < PERIOD_PERIOD_MAX)
break;
div++;
- if (div > PERIOD_CDIV_MAX)
+ if (div >= PERIOD_CDIV_MAX)
return -EINVAL;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] pwm: mxs: fix period divider computation
2015-02-18 13:06 [PATCH] pwm: mxs: fix period divider computation Gaetan Hug
@ 2015-03-02 12:32 ` Shawn Guo
2015-03-11 10:57 ` Thierry Reding
0 siblings, 1 reply; 3+ messages in thread
From: Shawn Guo @ 2015-03-02 12:32 UTC (permalink / raw)
To: Gaetan Hug; +Cc: thierry.reding, linux-pwm, linux-kernel, fabio.estevam
On Wed, Feb 18, 2015 at 02:06:34PM +0100, Gaetan Hug wrote:
> The driver computes which clock divider it sould be using from the
> requested period. This computation assumes that the link between the
> register value and the actual divider value is raising 2 to the power of
> the registry value.
>
> div = 1 << regvalue
>
> This is true only for the first 5 values out of 8. Next values are 64,
> 256 and, 1024 - instead of 32, 64, 128.
Just checked i.MX28 Reference Manual, and yes, this is the case.
> This affects only the users requesting a period > 0.04369s.
>
> Replace the computation with a look-up table.
Your SoB is missing here. Otherwise,
Acked-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/pwm/pwm-mxs.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c
> index f75ecb0..c65e183 100644
> --- a/drivers/pwm/pwm-mxs.c
> +++ b/drivers/pwm/pwm-mxs.c
> @@ -35,6 +35,8 @@
> #define PERIOD_CDIV(div) (((div) & 0x7) << 20)
> #define PERIOD_CDIV_MAX 8
>
> +static unsigned const int cdiv[PERIOD_CDIV_MAX] = {1, 2, 4, 8, 16, 64, 256, 1024};
> +
> struct mxs_pwm_chip {
> struct pwm_chip chip;
> struct clk *clk;
> @@ -54,13 +56,13 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>
> rate = clk_get_rate(mxs->clk);
> while (1) {
> - c = rate / (1 << div);
> + c = rate / cdiv[div];
> c = c * period_ns;
> do_div(c, 1000000000);
> if (c < PERIOD_PERIOD_MAX)
> break;
> div++;
> - if (div > PERIOD_CDIV_MAX)
> + if (div >= PERIOD_CDIV_MAX)
> return -EINVAL;
> }
>
> --
> 1.7.10.4
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pwm: mxs: fix period divider computation
2015-03-02 12:32 ` Shawn Guo
@ 2015-03-11 10:57 ` Thierry Reding
0 siblings, 0 replies; 3+ messages in thread
From: Thierry Reding @ 2015-03-11 10:57 UTC (permalink / raw)
To: Shawn Guo; +Cc: Gaetan Hug, linux-pwm, linux-kernel, fabio.estevam
[-- Attachment #1: Type: text/plain, Size: 967 bytes --]
On Mon, Mar 02, 2015 at 08:32:09PM +0800, Shawn Guo wrote:
> On Wed, Feb 18, 2015 at 02:06:34PM +0100, Gaetan Hug wrote:
> > The driver computes which clock divider it sould be using from the
> > requested period. This computation assumes that the link between the
> > register value and the actual divider value is raising 2 to the power of
> > the registry value.
> >
> > div = 1 << regvalue
> >
> > This is true only for the first 5 values out of 8. Next values are 64,
> > 256 and, 1024 - instead of 32, 64, 128.
>
> Just checked i.MX28 Reference Manual, and yes, this is the case.
>
> > This affects only the users requesting a period > 0.04369s.
> >
> > Replace the computation with a look-up table.
>
> Your SoB is missing here. Otherwise,
>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Gaetan,
can you resend with your Signed-off-by added? Or at least provide it
here? I can't really apply this without one.
Thierry
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