From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935448AbbCDHcJ (ORCPT ); Wed, 4 Mar 2015 02:32:09 -0500 Received: from mail-bl2on0116.outbound.protection.outlook.com ([65.55.169.116]:63616 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S935432AbbCDHcD (ORCPT ); Wed, 4 Mar 2015 02:32:03 -0500 Date: Wed, 4 Mar 2015 14:57:58 +0800 From: Peter Chen To: Greg KH CC: Liu Ying , , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , Fabio Estevam , , Subject: Re: [PATCH] video: mxsfb: Make sure axi clock is enabled when accessing registers Message-ID: <20150304065757.GB2689@shlinux2> References: <1425448735-21490-1-git-send-email-Ying.Liu@freescale.com> <20150304060817.GA12241@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150304060817.GA12241@kroah.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=peter.chen@freescale.com; vger.kernel.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.158.2;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(24454002)(199003)(51704005)(189002)(50466002)(46406003)(85426001)(50986999)(46102003)(86362001)(47776003)(33656002)(105606002)(33716001)(19580405001)(19580395003)(83506001)(6806004)(106466001)(23726002)(87936001)(97756001)(62966003)(92566002)(76176999)(110136001)(77096005)(104016003)(2950100001)(77156002)(54356999);DIR:OUT;SFP:1102;SCL:1;SRVR:BL2PR03MB243;H:az84smr01.freescale.net;FPR:;SPF:Fail;MLV:sfv;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB243; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006);SRVR:BL2PR03MB243;BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB243; X-Forefront-PRVS: 0505147DDB X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2015 06:58:07.1177 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB243 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 03, 2015 at 10:08:17PM -0800, Greg KH wrote: > On Wed, Mar 04, 2015 at 01:58:55PM +0800, Liu Ying wrote: > > The LCDIF engines embedded in i.MX6sl and i.MX6sx SoCs need the axi clock > > as the engine's system clock. The clock should be enabled when accessing > > LCDIF registers, otherwise the kernel would hang up. We should also keep > > the clock being enabled when the engine is being active to scan out frames > > from memory. This patch makes sure the axi clock is enabled when accessing > > registers so that the kernel hang up issue can be fixed. > > > > Reported-by: Peter Chen > > Signed-off-by: Liu Ying > > --- > > drivers/video/fbdev/mxsfb.c | 70 ++++++++++++++++++++++++++++++++++++--------- > > 1 file changed, 56 insertions(+), 14 deletions(-) > > > > This is not the correct way to submit patches for inclusion in the > stable kernel tree. Please read Documentation/stable_kernel_rules.txt > for how to do this properly. > > Hi Greg, I find this system hang issue at v4.0, and it should exist at v3.19 too. Do you mean Ying forget to add tag "Cc: stable@vger.kernel.org # 3.19" at commit log or you think this fix is too large? -- Best Regards, Peter Chen