From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752922AbbCDWJY (ORCPT ); Wed, 4 Mar 2015 17:09:24 -0500 Received: from mail-we0-f171.google.com ([74.125.82.171]:35919 "EHLO mail-we0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751899AbbCDWJX (ORCPT ); Wed, 4 Mar 2015 17:09:23 -0500 Date: Wed, 4 Mar 2015 23:09:13 +0100 From: Ingo Molnar To: Toshi Kani Cc: akpm@linux-foundation.org, hpa@zytor.com, tglx@linutronix.de, mingo@redhat.com, arnd@arndb.de, linux-mm@kvack.org, x86@kernel.org, linux-kernel@vger.kernel.org, dave.hansen@intel.com, Elliott@hp.com Subject: Re: [PATCH v3 3/6] mm: Change ioremap to set up huge I/O mappings Message-ID: <20150304220912.GA22518@gmail.com> References: <1425404664-19675-1-git-send-email-toshi.kani@hp.com> <1425404664-19675-4-git-send-email-toshi.kani@hp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1425404664-19675-4-git-send-email-toshi.kani@hp.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Toshi Kani wrote: > ioremap_pud_range() and ioremap_pmd_range() are changed to create > huge I/O mappings when their capability is enabled, and a request > meets required conditions -- both virtual & physical addresses are > aligned by their huge page size, and a requested range fufills their > huge page size. When pud_set_huge() or pmd_set_huge() returns zero, > i.e. no-operation is performed, the code simply falls back to the > next level. > > The changes are only enabled when CONFIG_HAVE_ARCH_HUGE_VMAP is > defined on the architecture. > > Signed-off-by: Toshi Kani > --- > include/asm-generic/pgtable.h | 15 +++++++++++++++ > lib/ioremap.c | 16 ++++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h > index 4d46085..bf6e86c 100644 > --- a/include/asm-generic/pgtable.h > +++ b/include/asm-generic/pgtable.h > @@ -6,6 +6,7 @@ > > #include > #include > +#include > > /* > * On almost all architectures and configurations, 0 can be used as the > @@ -697,4 +698,18 @@ static inline int pmd_protnone(pmd_t pmd) > #define io_remap_pfn_range remap_pfn_range > #endif > > +#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP > +int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); > +int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); > +#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ > +static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) > +{ > + return 0; > +} > +static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) > +{ > + return 0; > +} > +#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ > + > #endif /* _ASM_GENERIC_PGTABLE_H */ > diff --git a/lib/ioremap.c b/lib/ioremap.c > index 0ce18aa..3055ada 100644 > --- a/lib/ioremap.c > +++ b/lib/ioremap.c > @@ -81,6 +81,14 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr, > return -ENOMEM; > do { > next = pmd_addr_end(addr, end); > + > + if (ioremap_pmd_enabled() && > + ((next - addr) == PMD_SIZE) && > + IS_ALIGNED(phys_addr + addr, PMD_SIZE)) { > + if (pmd_set_huge(pmd, phys_addr + addr, prot)) > + continue; > + } > + > if (ioremap_pte_range(pmd, addr, next, phys_addr + addr, prot)) > return -ENOMEM; > } while (pmd++, addr = next, addr != end); > @@ -99,6 +107,14 @@ static inline int ioremap_pud_range(pgd_t *pgd, unsigned long addr, > return -ENOMEM; > do { > next = pud_addr_end(addr, end); > + > + if (ioremap_pud_enabled() && > + ((next - addr) == PUD_SIZE) && > + IS_ALIGNED(phys_addr + addr, PUD_SIZE)) { > + if (pud_set_huge(pud, phys_addr + addr, prot)) > + continue; > + } > + > if (ioremap_pmd_range(pud, addr, next, phys_addr + addr, prot)) > return -ENOMEM; > } while (pud++, addr = next, addr != end); Hm, so I don't see where you set the proper x86 PAT table attributes for the pmds. MTRR's are basically a legacy mechanism, the proper way to set cache attribute is PAT and I don't see where this generic code does that, but I might be missing something? Thanks, Ingo