From: Borislav Petkov <bp@alien8.de>
To: Ross Zwisler <ross.zwisler@linux.intel.com>
Cc: linux-kernel@vger.kernel.org,
H Peter Anvin <h.peter.anvin@intel.com>,
Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH] x86: Add kerneldoc for pcommit_sfence()
Date: Wed, 11 Mar 2015 21:18:30 +0100 [thread overview]
Message-ID: <20150311201830.GD3359@pd.tnic> (raw)
In-Reply-To: <1426097961-24921-1-git-send-email-ross.zwisler@linux.intel.com>
On Wed, Mar 11, 2015 at 12:19:21PM -0600, Ross Zwisler wrote:
> Add kerneldoc comments for pcommit_sfence() describing the purpose of
> the pcommit instruction and demonstrating the usage of that instruction.
>
> Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
> Cc: H Peter Anvin <h.peter.anvin@intel.com>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Borislav Petkov <bp@alien8.de>
> ---
> arch/x86/include/asm/special_insns.h | 37 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
> index aeb4666e0c0a..1ae81757c05b 100644
> --- a/arch/x86/include/asm/special_insns.h
> +++ b/arch/x86/include/asm/special_insns.h
> @@ -215,6 +215,43 @@ static inline void clwb(volatile void *__p)
> : [pax] "a" (p));
> }
>
> +/**
> + * pcommit_sfence() - persistent commit and fence
> + *
> + * The pcommit instruction ensures that data that has been flushed from the
> + * processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
> + * memory and is durable on the DIMM. The primary use case for this is
> + * persistent memory.
> + *
> + * This function shows how to properly use clwb/clflushopt/clflush and pcommit
> + * with appropriate fencing:
> + *
> + * void flush_and_commit_buffer(void *vaddr, unsigned int size)
> + * {
> + * unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1;
> + * char *vend = (char *)vaddr + size;
> + * char *p;
> + *
> + * for (p = (char *)((unsigned long)vaddr & ~clflush_mask);
> + * p < vend; p += boot_cpu_data.x86_clflush_size)
> + * clwb(p);
> + *
> + * // sfence to order clwb/clflushopt/clflush cache flushes
> + * // mfence via mb() also works
> + * wmb();
> + *
> + * // pcommit and the required sfence for ordering
> + * pcommit_sfence();
> + * }
> + *
> + * After this function completes the data pointed to by vaddr is has been
s/is //
I fixed it up while applying,
thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
next prev parent reply other threads:[~2015-03-11 20:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-11 18:19 [PATCH] x86: Add kerneldoc for pcommit_sfence() Ross Zwisler
2015-03-11 20:18 ` Borislav Petkov [this message]
2015-03-12 10:58 ` Ingo Molnar
2015-03-13 20:03 ` Ross Zwisler
2015-03-16 8:35 ` Ingo Molnar
2015-03-16 18:05 ` H. Peter Anvin
2015-03-17 8:11 ` Ingo Molnar
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