From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754635AbbCMKf2 (ORCPT ); Fri, 13 Mar 2015 06:35:28 -0400 Received: from foss.arm.com ([217.140.101.70]:51239 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751260AbbCMKfZ (ORCPT ); Fri, 13 Mar 2015 06:35:25 -0400 Date: Fri, 13 Mar 2015 10:34:54 +0000 From: Mark Rutland To: Kumar Gala Cc: "linux-arm-msm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "arm@kernel.org" , "devicetree@vger.kernel.org" , "heiko@sntech.de" Subject: Re: [PATCH v3 2/4] arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts Message-ID: <20150313103453.GA3592@leverpostej> References: <1426107080-29079-1-git-send-email-galak@codeaurora.org> <1426107080-29079-2-git-send-email-galak@codeaurora.org> <20150312170541.GE30145@leverpostej> <20150312182508.GF30145@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > Which of spin-table/psci are you planning on using for SMP support, and > > when would that be likely to appear? > > We have a qcom specific SMP enablement method for this device. This > was one of our first devices so it utilized as much from arm 32-bit as > possible. Implementation specific enable methods are something we really don't want to see for arm64. If PSCI is out of the question then a spin-table shim in your bootloader shouldn't be too hard to implement. > > Which exception level do CPUs enter the kernel? Even without a > > virt-capable GIC booting at EL2 is less work for the FW and gives the > > kernel a better chance of fixing things up (e.g. CNTVOFF). > > I think the enter in EL1. That's unfortunate, but so long as they are consistent, it's not the end of the world. Mark.