From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965081AbbCPUzF (ORCPT ); Mon, 16 Mar 2015 16:55:05 -0400 Received: from muru.com ([72.249.23.125]:37765 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751563AbbCPUy7 (ORCPT ); Mon, 16 Mar 2015 16:54:59 -0400 Date: Mon, 16 Mar 2015 13:50:09 -0700 From: Tony Lindgren To: Rostislav Lisovy Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Benoit Cousson , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Rostislav Lisovy Subject: Re: [PATCH 2/3] ARM: dts: am335x: Add DTS for ChiliSOM module Message-ID: <20150316205008.GB12397@atomide.com> References: <1423493285-4231-1-git-send-email-lisovy@jablotron.cz> <1423493285-4231-2-git-send-email-lisovy@jablotron.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1423493285-4231-2-git-send-email-lisovy@jablotron.cz> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Rostislav Lisovy [150209 06:51]: > Since this is a SOM (System on Module) that will be part > of another embedded board (and can't really exist on its own) > define it as a "dtsi" that will be included in the Device tree > describing the whole system later on. > > Hardware specification: > * AM335x SoC > * up to 512 MB RAM > * NAND Flash (8x interface, cs0) > * UART0 > * PMIC > * I2C0 (for PMIC) > * 1x Ethernet MAC Applying all three into omap-for-v4.1/dt with one change below. > --- /dev/null > +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi > + > +&gpmc { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&nandflash_pins>; > + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ > + nand@0,0 { > + reg = <0 0 0x01000000>; /* CS0 */ I've changed this to say just: reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ As for NAND the device has just one IO register. The 0x01000000 is the size of a minimum GPMC partition. Regards, Tony