From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755277AbbCXQd2 (ORCPT ); Tue, 24 Mar 2015 12:33:28 -0400 Received: from mga01.intel.com ([192.55.52.88]:62233 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752593AbbCXQdV (ORCPT ); Tue, 24 Mar 2015 12:33:21 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,459,1422950400"; d="scan'208";a="697037409" Date: Tue, 24 Mar 2015 21:59:17 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: Appana Durga Kedareswara Rao , "dan.j.williams@intel.com" , Michal Simek , Soren Brinkmann , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anirudha Sarangi , Srikanth Vemula , Srikanth Thokala Subject: Re: [PATCH v3 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support Message-ID: <20150324162917.GE32683@intel.com> References: <1425318926-28081-1-git-send-email-appanad@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 23, 2015 at 04:27:54PM +0000, Appana Durga Kedareswara Rao wrote: > Ping ! > > > -----Original Message----- > > From: Kedareswara rao Appana [mailto:appana.durga.rao@xilinx.com] > > Sent: Monday, March 02, 2015 11:25 PM > > To: dan.j.williams@intel.com; vinod.koul@intel.com; Michal Simek; Soren > > Brinkmann > > Cc: dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > > kernel@vger.kernel.org; Appana Durga Kedareswara Rao; Anirudha Sarangi; > > Srikanth Vemula; Srikanth Thokala > > Subject: [PATCH v3 2/2] dma: Add Xilinx AXI Central Direct Memory Access > > Engine driver support > > > > This is the driver for the AXI Central Direct Memory Access (AXI > > CDMA) core, which is a soft Xilinx IP core that provides high-bandwidth Direct > > Memory Access (DMA) between a memory-mapped source address and a > > memory-mapped destination address. Somehow I dont seem to have this in my queue, so can you please resend this one for me -- ~Vinod