From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751850AbbCYWKI (ORCPT ); Wed, 25 Mar 2015 18:10:08 -0400 Received: from down.free-electrons.com ([37.187.137.238]:54392 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751220AbbCYWKG (ORCPT ); Wed, 25 Mar 2015 18:10:06 -0400 Date: Wed, 25 Mar 2015 15:07:46 -0700 From: Maxime Ripard To: Chen-Yu Tsai Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Hans de Goede , Marcus Cooper Subject: Re: [PATCH 0/3] ARM: dts: sun6i: Enable cpufreq support for A31/A31s Message-ID: <20150325220746.GQ23664@lukather> References: <1427317489-708-1-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="1WN/MJ7JJGqVzwIW" Content-Disposition: inline In-Reply-To: <1427317489-708-1-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --1WN/MJ7JJGqVzwIW Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 26, 2015 at 05:04:46AM +0800, Chen-Yu Tsai wrote: > Hi everyone, >=20 > This series adds the DT parts of cpufreq support, clock references, therm= al > zones and OPPs, for sun6i. This is based on sunxi/for-next (6bcf44d5edfb). > Required (sun4i-ts) driver support is already in v4.0-rc1. >=20 > Patch 1 moves the ahb1 assigned-clocks reparenting properties from the dma > controller node to the ahb1 clock node. This matches what we've done for > sun5i and sun7i. The purpose of this is to clock ahb1 from a stable clock > as soon as possible, to prevent hrtimer miscalculation/instability. >=20 > Patch 2 adds the clock reference and OPPs for the cpu cluster. >=20 > Patch 3 adds the thermal zones for CPU passive (cpufreq limiting) cooling. >=20 > I've tested this on my Sinlinx SinA31s (not yet mainlined). The highest > OPP matches the default CPU clock/voltage setting found in mainline > u-boot. However the Mele I7 fex file specifies a slightly higher voltage > for 1008 MHz. If the default setting is not stable enough for the Mele > I7, it should be overridden in the board dts file. >=20 > This series does not cover A31/A31s revision D, which seems to have lower > voltage requirements. At the moment no one has seen them. Applied all three, thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --1WN/MJ7JJGqVzwIW Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVEzGyAAoJEBx+YmzsjxAg3NQQAKJhV1CgAmpuv4ctFSyoCZOD c26rPkSKDfr8PUpflNKrQ5ETrowZejJAjWle1nZs5TUdhm9Kr2c8tJn+zG3LCcuZ HxNXX0kQrFf6uOdCZis4nU4UwWUKlsWmoBHtonwffErnBfd/alNcu3t0bsyOosks ZXkQbDcC7FROtrljtZ37LmC9xgGEMfdvwmXbYPpgh1PTgyn8p1tG3u6CJg0AVVxf czapiIebn2KNT3ZoSQofuZZBCy+tcvlw07SxHur/secH17Dd+CgVXGX8vUGgkL2M RGGG3i2o344FGN/KJTcHrgzCjQ1d1/yV63FphL4bA4f/elvASNMyrRmcGylIK9A7 ZhncpOrBw2qQyjdt2JBtUY1Ug1EnMjuXSg5LOOyHVKdj3sYI6dU36jFHErYO1dwn Gw6NHre6Rv4aS7GZnXj/GkpLQxCyhO2OlNbZuxelh5UNRgSLUDJtP1bpmNQ4KyrA TPtwFaXO2PGWKebjVn46iMKJwMac/1gW9rInz4pVjhHlis+f2mVCWFPmlinEER3p dim7rvBNbvx/G6A+AjKRPenm2aB8JrpBN0UoZqM6Gx+/59fyWVeSPQ0ITPxYLn9C ZBoTuSlZXkVjMWcG7nipVZSjrSBKZYdBm4yGHWK/vX8uq/WQ/K1ZnBltztQfOJNP z6UC04sU6A5FAMAVNPMv =ZH+y -----END PGP SIGNATURE----- --1WN/MJ7JJGqVzwIW--