[PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

[PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

[kan.liang]

From: Kan Liang <kan.liang@intel.com>

Same as Haswell, Broadwell also support LBR callstack.

Signed-off-by: Kan Liang <kan.liang@intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index fc6dbc4..4b61fe9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
 		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
 									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
 
-		intel_pmu_lbr_init_snb();
+		intel_pmu_lbr_init_hsw();
 
 		x86_pmu.event_constraints = intel_bdw_event_constraints;
 		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
-- 
1.8.3.1

Re: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

[Andi Kleen]

On Thu, Apr 02, 2015 at 04:12:57AM -0400, kan.liang@intel.com wrote:
> From: Kan Liang <kan.liang@intel.com>
> 
> Same as Haswell, Broadwell also support LBR callstack.
> 
> Signed-off-by: Kan Liang <kan.liang@intel.com>

Thanks looks good.

Acked-by: Andi Kleen <ak@linux.intel.com>

-Andi


> ---
>  arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index fc6dbc4..4b61fe9 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
>  		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
>  									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
>  
> -		intel_pmu_lbr_init_snb();
> +		intel_pmu_lbr_init_hsw();
>  
>  		x86_pmu.event_constraints = intel_bdw_event_constraints;
>  		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
> -- 
> 1.8.3.1
> 

-- 
ak@linux.intel.com -- Speaking for myself only

[tip:perf/urgent] perf/x86/intel: Add Broadwell support for the LBR callstack

[tip-bot for Kan Liang]

Commit-ID:  78d504bcd769cc496f63b626f507039eab2316b7
Gitweb:     http://git.kernel.org/tip/78d504bcd769cc496f63b626f507039eab2316b7
Author:     Kan Liang <kan.liang@intel.com>
AuthorDate: Thu, 2 Apr 2015 04:12:57 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Fri, 17 Apr 2015 09:59:07 +0200

perf/x86/intel: Add Broadwell support for the LBR callstack

Same as Haswell, Broadwell also support the LBR callstack.

Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Andi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/1427962377-40955-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 9da2400..219d3fb 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -3275,7 +3275,7 @@ __init int intel_pmu_init(void)
 		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
 									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
 
-		intel_pmu_lbr_init_snb();
+		intel_pmu_lbr_init_hsw();
 
 		x86_pmu.event_constraints = intel_bdw_event_constraints;
 		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;