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From: Andrew Lunn <andrew@lunn.ch>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Vinod Koul <vinod.koul@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Gregory Clement <gregory.clement@free-electrons.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
	Lior Amsalem <alior@marvell.com>,
	Thomas Petazzoni <thomas@free-electrons.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	"David S. Miller" <davem@davemloft.net>
Subject: Re: [PATCH 6/8] async_tx: adding mult and sum_product flags
Date: Tue, 12 May 2015 18:05:35 +0200	[thread overview]
Message-ID: <20150512160535.GK19927@lunn.ch> (raw)
In-Reply-To: <1431445063-20226-7-git-send-email-maxime.ripard@free-electrons.com>

On Tue, May 12, 2015 at 05:37:41PM +0200, Maxime Ripard wrote:
> From: Lior Amsalem <alior@marvell.com>
> 
> Some engines (like Marvell mv_xor) do not support mult and sum_product
> operations as part of the pq support.
> 
> This patch adds new flags: DMA_PREP_PQ_MULT & DMA_PREP_PQ_SUM_PRODUCT these
> flags helps the driver identify such operations.
> 
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  crypto/async_tx/async_raid6_recov.c | 4 ++--
>  include/linux/dmaengine.h           | 4 ++++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/crypto/async_tx/async_raid6_recov.c b/crypto/async_tx/async_raid6_recov.c
> index 934a84981495..2db5486fd873 100644
> --- a/crypto/async_tx/async_raid6_recov.c
> +++ b/crypto/async_tx/async_raid6_recov.c
> @@ -47,7 +47,7 @@ async_sum_product(struct page *dest, struct page **srcs, unsigned char *coef,
>  		struct device *dev = dma->dev;
>  		dma_addr_t pq[2];
>  		struct dma_async_tx_descriptor *tx;
> -		enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
> +		enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P | DMA_PREP_PQ_SUM_PRODUCT;
>  
>  		if (submit->flags & ASYNC_TX_FENCE)
>  			dma_flags |= DMA_PREP_FENCE;
> @@ -111,7 +111,7 @@ async_mult(struct page *dest, struct page *src, u8 coef, size_t len,
>  		dma_addr_t dma_dest[2];
>  		struct device *dev = dma->dev;
>  		struct dma_async_tx_descriptor *tx;
> -		enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
> +		enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P | DMA_PREP_PQ_MULT;
>  
>  		if (submit->flags & ASYNC_TX_FENCE)
>  			dma_flags |= DMA_PREP_FENCE;
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index ad419757241f..f19ecebb4d3f 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -174,6 +174,8 @@ struct dma_interleaved_template {
>   *  operation it continues the calculation with new sources
>   * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
>   *  on the result of this operation
> + * @DMA_PREP_PQ_MULT - tell the driver that this is a mult request
> + * @DMA_PREP_PQ_SUM_PRODUCT - tell the driver that this is a sum product request
>   */
>  enum dma_ctrl_flags {
>  	DMA_PREP_INTERRUPT = (1 << 0),
> @@ -182,6 +184,8 @@ enum dma_ctrl_flags {
>  	DMA_PREP_PQ_DISABLE_Q = (1 << 3),
>  	DMA_PREP_CONTINUE = (1 << 4),
>  	DMA_PREP_FENCE = (1 << 5),
> +	DMA_PREP_PQ_MULT = (1 << 10),
> +	DMA_PREP_PQ_SUM_PRODUCT = (1 << 11),

Any reason for skipping 6 to 9?

    Andrew

  reply	other threads:[~2015-05-12 16:10 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-12 15:37 [PATCH 0/8] ARM: mvebu: Add support for RAID6 PQ offloading Maxime Ripard
2015-05-12 15:37 ` [PATCH 1/8] dmaengine: mv_xor: Rename function for consistent naming Maxime Ripard
2015-05-12 15:37 ` [PATCH 2/8] dmaengine: mv_xor: add support for a38x command in descriptor mode Maxime Ripard
2015-05-12 15:49   ` Arnd Bergmann
2015-05-12 15:54     ` Thomas Petazzoni
2015-05-12 16:03       ` Arnd Bergmann
2015-05-13  8:15     ` Maxime Ripard
2015-05-13  8:46       ` Arnd Bergmann
2015-05-12 15:49   ` Thomas Petazzoni
2015-05-12 15:58     ` Andrew Lunn
2015-05-12 16:05       ` Thomas Petazzoni
2015-05-13  8:23         ` Maxime Ripard
2015-05-12 15:37 ` [PATCH 3/8] dmaengine: mv_xor: Enlarge descriptor pool size Maxime Ripard
2015-05-12 15:37 ` [PATCH 4/8] dmaengine: mv_xor: improve descriptors list handling and reduce locking Maxime Ripard
2015-05-12 15:37 ` [PATCH 5/8] dmaengine: mv_xor: bug fix for racing condition in descriptors cleanup Maxime Ripard
2015-05-12 15:51   ` Thomas Petazzoni
2015-05-12 15:37 ` [PATCH 6/8] async_tx: adding mult and sum_product flags Maxime Ripard
2015-05-12 16:05   ` Andrew Lunn [this message]
2015-05-13  8:45     ` Maxime Ripard
2015-05-12 15:37 ` [PATCH 7/8] dmaengine: mv_xor: add support for a38x RAID6 support Maxime Ripard
2015-05-12 15:37 ` [PATCH 8/8] ARM: mvebu: a38x: Enable A38x XOR engine features Maxime Ripard
2015-05-12 16:13   ` Andrew Lunn
2015-05-13  7:16     ` Lior Amsalem
2015-05-13  8:33       ` Maxime Ripard
2015-05-12 16:05 ` [PATCH 0/8] ARM: mvebu: Add support for RAID6 PQ offloading Dan Williams
2015-05-13  9:17   ` Maxime Ripard
2015-05-13 16:00     ` Dan Williams
2015-05-18  9:14       ` Maxime Ripard
2015-05-18 17:06         ` Dan Williams
2015-05-26  9:45           ` Maxime Ripard
2015-05-26 16:31             ` Dan Williams
2015-05-27 11:52               ` Boaz Harrosh
2015-06-02 14:41               ` Maxime Ripard

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