From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752897AbbENGym (ORCPT ); Thu, 14 May 2015 02:54:42 -0400 Received: from mail-bl2on0135.outbound.protection.outlook.com ([65.55.169.135]:63664 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751324AbbENGyi (ORCPT ); Thu, 14 May 2015 02:54:38 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; intel.com; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NOBV6X-08-7R0-02 X-M-MSG: Date: Thu, 14 May 2015 14:54:52 +0800 From: Huang Rui To: Len Brown , "Rafael J. Wysocki" CC: , Fengguang Wu , Aaron Lu , Tony Li Subject: Mwait usage on AMD processors Message-ID: <20150514065451.GA29830@hr-slim.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11OLC005;1:APtF3ByEixf0Qiz+AvddNoOZrhVZCU9UWDdO3YRVIPgk4pMiDw3C9Htcr9Uy+A59wk3B1WkAX5XUrA5DJjpCUXLz7IGSrFWZcpayyoU1vJFrThC7n+wnQZpsnp4G8CuEf2Ua4snpeHlW/KxyzD3qYCRWvzX+05mHSWlDNPSmBZf4284T7FnF1M5bXOoRh3G+RuUHSZRmorER1Qvw53AefbMwlnGxRdZgwv+lgzqpgvId/G2RSssoKJCrtvZDbROmEOggLJzDnOzJeC5FRG/vNxyO5g7GY23jsC4s2UnAjrF+ETWqez/R0//DRZulfg4qJDwpOVKaIEr2VSDubGBZmw== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(164054003)(189002)(199003)(106466001)(50466002)(87936001)(229853001)(33656002)(86362001)(46406003)(97756001)(54356999)(50986999)(47776003)(4001350100001)(83506001)(62966003)(77156002)(23726002)(92566002)(53416004)(77096005)(5001770100001)(189998001)(101416001)(46102003)(105586002);DIR:OUT;SFP:1102;SCL:1;SRVR:BN1PR02MB072;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB072; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN1PR02MB072;BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB072; X-Forefront-PRVS: 0576145E86 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2015 06:54:35.0826 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR02MB072 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Len, Rafael, and all, AMD proposed a new instruction named mwaitx. This is an extension of mwait with a configurable timer (mwaitx = mwait + timer). And mwaitx will act as mwait if timer is disabled. However, mwait/mwaitx cannot let cpu core go to C1 state at current AMD processors, but has less power consumption even at C0 while core is waiting. As you know, mwait/mwaitx would have better performance than halt. So could we propose an implementation to use mwaitx at idle call in boot phase and cpuidle driver after boot phase. And the mwaitx idle is exposed to user as an optional kernel parameter(idle=...), and decided by user. Any comments are warm for me :) Thanks, Rui