From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751697AbbEQTAh (ORCPT ); Sun, 17 May 2015 15:00:37 -0400 Received: from down.free-electrons.com ([37.187.137.238]:38336 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751357AbbEQTAQ (ORCPT ); Sun, 17 May 2015 15:00:16 -0400 Date: Sun, 17 May 2015 16:51:46 +0200 From: Maxime Ripard To: Chen-Yu Tsai Cc: Nicolas Pitre , Dave Martin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80 Message-ID: <20150517145146.GK4004@lukather> References: <1431583811-25780-1-git-send-email-wens@csie.org> <1431583811-25780-3-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="M1akecbV8LB7u7K0" Content-Disposition: inline In-Reply-To: <1431583811-25780-3-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --M1akecbV8LB7u7K0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: > The A80 includes an ARM CCI-400 interconnect to support multi-cluster > CPU caches. >=20 > Also add the default clock frequency for the CPUs. >=20 > Signed-off-by: Chen-Yu Tsai > --- > arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 46 insertions(+) >=20 > diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a= 80.dtsi > index ca272e92b85d..200e712fbf0e 100644 > --- a/arch/arm/boot/dts/sun9i-a80.dtsi > +++ b/arch/arm/boot/dts/sun9i-a80.dtsi > @@ -58,48 +58,64 @@ > cpu0: cpu@0 { > compatible =3D "arm,cortex-a7"; > device_type =3D "cpu"; > + cci-control-port =3D <&cci_control0>; > + clock-frequency =3D <12000000>; > reg =3D <0x0>; > }; > =20 > cpu1: cpu@1 { > compatible =3D "arm,cortex-a7"; > device_type =3D "cpu"; > + cci-control-port =3D <&cci_control0>; > + clock-frequency =3D <12000000>; > reg =3D <0x1>; > }; > =20 > cpu2: cpu@2 { > compatible =3D "arm,cortex-a7"; > device_type =3D "cpu"; > + cci-control-port =3D <&cci_control0>; > + clock-frequency =3D <12000000>; > reg =3D <0x2>; > }; > =20 > cpu3: cpu@3 { > compatible =3D "arm,cortex-a7"; > device_type =3D "cpu"; > + cci-control-port =3D <&cci_control0>; > + clock-frequency =3D <12000000>; > reg =3D <0x3>; > }; > =20 > cpu4: cpu@100 { > compatible =3D "arm,cortex-a15"; > device_type =3D "cpu"; > + cci-control-port =3D <&cci_control1>; > + clock-frequency =3D <9000000>; Isn't the clock frequency property is supposed to be the maximum frequency of that CPU in Linux? It looks odd that the A15 are clocked at a lower frequency than the A7... Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --M1akecbV8LB7u7K0 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJVWKsCAAoJEBx+YmzsjxAgRTMP+QHL+YTszzElz7v8o9ZTGQai zTzNG/0ZqULfjl6TI+J9edsFS4KMjJCNk/r80dKzOTeHcYJmN7PvJSKPssZvWwj4 ZMSn3eY+koITNRSa9VX5n1YKmvLrZxqFuKxJrUD8AyIpzVvjMbYukE6c56JUXUZO JXS8GHlnJOTPcoFo1NSwFs5xskD8fLk4Np7GTYviPbSQ2i2GppAbWxSs3W51yS3A bWXzt+de0J1nIn/EOHkvGTX5AnC2aLVBiZSPlJvakdVyF3FRFdPomLH4L6pc59ey Q/agbeqF2e8GK+eNgJaA+8fIeOIzg8qvNebNW9ql5h08ItAT/PCVHSM752ex3mo8 4yQQhXvpkgK6F4FMeGuucqV6yqw4EA9UaijhosTcH6sV8grWciNx4RNQxlvUDQfc 1XA6g49hyT3EaG+M+bzTTe+k47eBy+Oay/dSnKIkA3LlS4sz0Vhhd7c4Frg5+15H oEHNYd6hQQ/H/FKBM/7NQiCFx00fVP71rzU+NK0xyOoXfFPJlUaAeflsUHKpL401 hvyRJEikpj6Pgk7gdOuROFAvihjfkdzRDm+C0uD0eOETnOLCtMuHsBaRC/lYlaXm K7CPaIKh5rxey6Kkd6yApBXJX7YlSUE9BJYsyb9M99UQImjwEB2js0n9aXgpN7AQ 3t9/TnKAzul5s+usa+yY =hqj7 -----END PGP SIGNATURE----- --M1akecbV8LB7u7K0--