From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
x86@kernel.org, Matt Fleming <matt.fleming@intel.com>,
Will Auld <will.auld@intel.com>,
Kanaka Juvva <kanaka.d.juvva@intel.com>
Subject: [patch 2/6] x86, perf, cqm: Use proper data type
Date: Tue, 19 May 2015 00:00:51 -0000 [thread overview]
Message-ID: <20150518235149.919350144@linutronix.de> (raw)
In-Reply-To: 20150518234114.574556332@linutronix.de
[-- Attachment #1: x86-perf-cqm-use-proper-data-types.patch --]
[-- Type: text/plain, Size: 1493 bytes --]
int is really not a proper data type for a MSR. Use u32 to make it
clear that we are dealing with a 32bit unsigned hardware value.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 4 ++--
include/linux/perf_event.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -18,7 +18,7 @@ static unsigned int cqm_l3_scale; /* sup
struct intel_cqm_state {
raw_spinlock_t lock;
- int rmid;
+ u32 rmid;
int cnt;
};
@@ -962,7 +962,7 @@ out:
static void intel_cqm_event_start(struct perf_event *event, int mode)
{
struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);
- unsigned int rmid = event->hw.cqm_rmid;
+ u32 rmid = event->hw.cqm_rmid;
unsigned long flags;
if (!(event->hw.cqm_state & PERF_HES_STOPPED))
Index: linux/include/linux/perf_event.h
===================================================================
--- linux.orig/include/linux/perf_event.h
+++ linux/include/linux/perf_event.h
@@ -124,7 +124,7 @@ struct hw_perf_event {
};
struct { /* intel_cqm */
int cqm_state;
- int cqm_rmid;
+ u32 cqm_rmid;
struct list_head cqm_events_entry;
struct list_head cqm_groups_entry;
struct list_head cqm_group_entry;
next prev parent reply other threads:[~2015-05-19 0:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-19 0:00 [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Thomas Gleixner
2015-05-19 0:00 ` [patch 1/6] x86, perf, cqm: Document PQR MSR abuse Thomas Gleixner
2015-05-19 11:53 ` Matt Fleming
2015-05-27 10:02 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19 0:00 ` Thomas Gleixner [this message]
2015-05-19 8:58 ` [patch 2/6] x86, perf, cqm: Use proper data type Matt Fleming
2015-05-19 13:03 ` Thomas Gleixner
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: Use proper data types tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 3/6] x86, perf, cqm: Remove pointless spinlock from state cache Thomas Gleixner
2015-05-19 9:13 ` Matt Fleming
2015-05-19 10:51 ` Peter Zijlstra
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-06-05 18:13 ` [patch 3/6] x86, perf, cqm: " Juvva, Kanaka D
2015-05-19 0:00 ` [patch 4/6] x86, perf, cqm: Avoid pointless msr write Thomas Gleixner
2015-05-19 9:17 ` Matt Fleming
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 5/6] x86, perf, cqm: Remove useless wrapper function Thomas Gleixner
2015-05-19 9:18 ` Matt Fleming
2015-05-27 10:04 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state Thomas Gleixner
2015-05-19 11:54 ` Matt Fleming
2015-05-19 12:59 ` Thomas Gleixner
2015-05-27 10:04 ` [tip:perf/core] perf/x86/intel/cqm: Add storage for 'closid' and clean up 'struct intel_pqr_state' tip-bot for Thomas Gleixner
2015-05-19 7:42 ` [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Peter Zijlstra
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